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Converting PRESENTATION_ExSyn
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Krystine Sherwin
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31 changed files with 442 additions and 517 deletions
438
docs/source/getting_started/typical_phases.rst
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438
docs/source/getting_started/typical_phases.rst
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Typical Phases of a Synthesis Flow
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----------------------------------
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- Reading and elaborating the design
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- Higher-level synthesis and optimization
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- Converting ``always``-blocks to logic and registers
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- Perform coarse-grain optimizations (resource sharing, const folding, ...)
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- Handling of memories and other coarse-grain blocks
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- Extracting and optimizing finite state machines
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- Convert remaining logic to bit-level logic functions
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- Perform optimizations on bit-level logic functions
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- Map bit-level logic gates and registers to cell library
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- Write results to output file
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Reading the design
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~~~~~~~~~~~~~~~~~~
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.. code-block:: yoscrypt
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read_verilog file1.v
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read_verilog -I include_dir -D enable_foo -D WIDTH=12 file2.v
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read_verilog -lib cell_library.v
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verilog_defaults -add -I include_dir
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read_verilog file3.v
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read_verilog file4.v
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verilog_defaults -clear
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verilog_defaults -push
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verilog_defaults -add -I include_dir
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read_verilog file5.v
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read_verilog file6.v
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verilog_defaults -pop
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Design elaboration
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~~~~~~~~~~~~~~~~~~
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During design elaboration Yosys figures out how the modules are hierarchically
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connected. It also re-runs the AST parts of the Verilog frontend to create all
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needed variations of parametric modules.
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.. code-block:: yoscrypt
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# simplest form. at least this version should be used after reading all input files
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#
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hierarchy
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# recommended form. fails if parts of the design hierarchy are missing, removes
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# everything that is unreachable from the top module, and marks the top module.
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#
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hierarchy -check -top top_module
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The ``proc`` command
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~~~~~~~~~~~~~~~~~~~~~~
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The Verilog frontend converts ``always``-blocks to RTL netlists for the
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expressions and "processess" for the control- and memory elements.
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The ``proc`` command transforms this "processess" to netlists of RTL multiplexer
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and register cells.
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The ``proc`` command is actually a macro-command that calls the following other
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commands:
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.. code-block:: yoscrypt
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proc_clean # remove empty branches and processes
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proc_rmdead # remove unreachable branches
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proc_init # special handling of "initial" blocks
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proc_arst # identify modeling of async resets
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proc_mux # convert decision trees to multiplexer networks
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proc_dff # extract registers from processes
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proc_clean # if all went fine, this should remove all the processes
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Many commands can not operate on modules with "processess" in them. Usually a
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call to ``proc`` is the first command in the actual synthesis procedure after
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design elaboration.
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Example
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^^^^^^^
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.. literalinclude:: ../../resources/PRESENTATION_ExSyn/proc_01.v
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:language: verilog
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:caption: ``docs/resources/PRESENTATION_ExSyn/proc_01.v``
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.. literalinclude:: ../../resources/PRESENTATION_ExSyn/proc_01.ys
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:language: yoscrypt
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:caption: ``docs/resources/PRESENTATION_ExSyn/proc_01.ys``
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.. figure:: ../../images/res/PRESENTATION_ExSyn/proc_01.*
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:class: width-helper
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.. figure:: ../../images/res/PRESENTATION_ExSyn/proc_02.*
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:class: width-helper
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.. literalinclude:: ../../resources/PRESENTATION_ExSyn/proc_02.v
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:language: verilog
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:caption: ``docs/resources/PRESENTATION_ExSyn/proc_02.v``
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.. literalinclude:: ../../resources/PRESENTATION_ExSyn/proc_02.ys
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:language: yoscrypt
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:caption: ``docs/resources/PRESENTATION_ExSyn/proc_02.ys``
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.. figure:: ../../images/res/PRESENTATION_ExSyn/proc_03.*
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:class: width-helper
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.. literalinclude:: ../../resources/PRESENTATION_ExSyn/proc_03.ys
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:language: yoscrypt
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:caption: ``docs/resources/PRESENTATION_ExSyn/proc_03.ys``
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.. literalinclude:: ../../resources/PRESENTATION_ExSyn/proc_03.v
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:language: verilog
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:caption: ``docs/resources/PRESENTATION_ExSyn/proc_03.v``
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The ``opt`` command
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~~~~~~~~~~~~~~~~~~~~~
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The ``opt`` command implements a series of simple optimizations. It also is a
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macro command that calls other commands:
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.. code-block:: yoscrypt
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opt_expr # const folding and simple expression rewriting
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opt_merge -nomux # merging identical cells
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do
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opt_muxtree # remove never-active branches from multiplexer tree
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opt_reduce # consolidate trees of boolean ops to reduce functions
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opt_merge # merging identical cells
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opt_rmdff # remove/simplify registers with constant inputs
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opt_clean # remove unused objects (cells, wires) from design
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opt_expr # const folding and simple expression rewriting
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while [changed design]
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The command ``clean`` can be used as alias for ``opt_clean``. And ``;;`` can be
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used as shortcut for ``clean``. For example:
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.. code-block:: yoscrypt
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proc; opt; memory; opt_expr;; fsm;;
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Example
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^^^^^^^
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.. figure:: ../../images/res/PRESENTATION_ExSyn/opt_01.*
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:class: width-helper
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.. literalinclude:: ../../resources/PRESENTATION_ExSyn/opt_01.ys
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:language: yoscrypt
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:caption: ``docs/resources/PRESENTATION_ExSyn/opt_01.ys``
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.. literalinclude:: ../../resources/PRESENTATION_ExSyn/opt_01.v
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:language: verilog
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:caption: ``docs/resources/PRESENTATION_ExSyn/opt_01.v``
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.. figure:: ../../images/res/PRESENTATION_ExSyn/opt_02.*
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:class: width-helper
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.. literalinclude:: ../../resources/PRESENTATION_ExSyn/opt_02.ys
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:language: yoscrypt
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:caption: ``docs/resources/PRESENTATION_ExSyn/opt_02.ys``
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.. literalinclude:: ../../resources/PRESENTATION_ExSyn/opt_02.v
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:language: verilog
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:caption: ``docs/resources/PRESENTATION_ExSyn/opt_02.v``
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.. figure:: ../../images/res/PRESENTATION_ExSyn/opt_03.*
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:class: width-helper
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.. literalinclude:: ../../resources/PRESENTATION_ExSyn/opt_03.ys
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:language: yoscrypt
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:caption: ``docs/resources/PRESENTATION_ExSyn/opt_03.ys``
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.. literalinclude:: ../../resources/PRESENTATION_ExSyn/opt_03.v
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:language: verilog
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:caption: ``docs/resources/PRESENTATION_ExSyn/opt_03.v``
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.. figure:: ../../images/res/PRESENTATION_ExSyn/opt_04.*
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:class: width-helper
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.. literalinclude:: ../../resources/PRESENTATION_ExSyn/opt_04.v
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:language: verilog
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:caption: ``docs/resources/PRESENTATION_ExSyn/opt_04.v``
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.. literalinclude:: ../../resources/PRESENTATION_ExSyn/opt_04.ys
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:language: yoscrypt
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:caption: ``docs/resources/PRESENTATION_ExSyn/opt_04.ys``
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When to use ``opt`` or ``clean``
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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Usually it does not hurt to call ``opt`` after each regular command in the
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synthesis script. But it increases the synthesis time, so it is favourable to
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only call ``opt`` when an improvement can be achieved.
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The designs in ``yosys-bigsim`` are a good playground for experimenting with the
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effects of calling ``opt`` in various places of the flow.
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It generally is a good idea to call ``opt`` before inherently expensive commands
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such as ``sat`` or ``freduce``, as the possible gain is much higher in this
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cases as the possible loss.
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The ``clean`` command on the other hand is very fast and many commands leave a
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mess (dangling signal wires, etc). For example, most commands do not remove any
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wires or cells. They just change the connections and depend on a later call to
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clean to get rid of the now unused objects. So the occasional ``;;`` is a good
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idea in every synthesis script.
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The ``memory`` command
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~~~~~~~~~~~~~~~~~~~~~~~~
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In the RTL netlist, memory reads and writes are individual cells. This makes
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consolidating the number of ports for a memory easier. The ``memory``
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transforms memories to an implementation. Per default that is logic for address
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decoders and registers. It also is a macro command that calls other commands:
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.. code-block:: yoscrypt
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# this merges registers into the memory read- and write cells.
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memory_dff
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# this collects all read and write cells for a memory and transforms them
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# into one multi-port memory cell.
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memory_collect
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# this takes the multi-port memory cell and transforms it to address decoder
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# logic and registers. This step is skipped if "memory" is called with -nomap.
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memory_map
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Usually it is preferred to use architecture-specific RAM resources for memory.
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For example:
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.. code-block:: yoscrypt
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memory -nomap; techmap -map my_memory_map.v; memory_map
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Example
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^^^^^^^
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.. figure:: ../../images/res/PRESENTATION_ExSyn/memory_01.*
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:class: width-helper
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.. literalinclude:: ../../resources/PRESENTATION_ExSyn/memory_01.ys
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:language: yoscrypt
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:caption: ``docs/resources/PRESENTATION_ExSyn/memory_01.ys``
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.. literalinclude:: ../../resources/PRESENTATION_ExSyn/memory_01.v
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:language: verilog
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:caption: ``docs/resources/PRESENTATION_ExSyn/memory_01.v``
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.. figure:: ../../images/res/PRESENTATION_ExSyn/memory_02.*
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:class: width-helper
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.. literalinclude:: ../../resources/PRESENTATION_ExSyn/memory_02.v
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:language: verilog
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:caption: ``docs/resources/PRESENTATION_ExSyn/memory_02.v``
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.. literalinclude:: ../../resources/PRESENTATION_ExSyn/memory_02.ys
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:language: yoscrypt
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:caption: ``docs/resources/PRESENTATION_ExSyn/memory_02.ys``
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The ``fsm`` command
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~~~~~~~~~~~~~~~~~~~~~
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The ``fsm`` command identifies, extracts, optimizes (re-encodes), and
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re-synthesizes finite state machines. It again is a macro that calls
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a series of other commands:
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.. code-block:: yoscrypt
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fsm_detect # unless got option -nodetect
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fsm_extract
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fsm_opt
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clean
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fsm_opt
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fsm_expand # if got option -expand
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clean # if got option -expand
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fsm_opt # if got option -expand
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fsm_recode # unless got option -norecode
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fsm_info
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fsm_export # if got option -export
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fsm_map # unless got option -nomap
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Some details on the most important commands from the ``fsm_*`` group:
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The ``fsm_detect`` command identifies FSM state registers and marks them with
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the ``(* fsm_encoding = "auto" *)`` attribute, if they do not have the
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``fsm_encoding`` set already. Mark registers with ``(* fsm_encoding = "none"
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*)`` to disable FSM optimization for a register.
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The ``fsm_extract`` command replaces the entire FSM (logic and state registers)
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with a ``$fsm`` cell.
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The commands ``fsm_opt`` and ``fsm_recode`` can be used to optimize the FSM.
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Finally the ``fsm_map`` command can be used to convert the (optimized) ``$fsm``
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cell back to logic and registers.
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The ``techmap`` command
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~~~~~~~~~~~~~~~~~~~~~~~~~
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.. figure:: ../../images/res/PRESENTATION_ExSyn/techmap_01.*
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:class: width-helper
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The ``techmap`` command replaces cells with implementations given as
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verilog source. For example implementing a 32 bit adder using 16 bit adders:
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.. literalinclude:: ../../resources/PRESENTATION_ExSyn/techmap_01_map.v
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:language: verilog
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:caption: ``docs/resources/PRESENTATION_ExSyn/techmap_01_map.v``
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.. literalinclude:: ../../resources/PRESENTATION_ExSyn/techmap_01.v
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:language: verilog
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:caption: ``docs/resources/PRESENTATION_ExSyn/techmap_01.v``
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.. literalinclude:: ../../resources/PRESENTATION_ExSyn/techmap_01.ys
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:language: yoscrypt
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:caption: ``docs/resources/PRESENTATION_ExSyn/techmap_01.ys``
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stdcell mapping
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^^^^^^^^^^^^^^^
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When ``techmap`` is used without a map file, it uses a built-in map file to map
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all RTL cell types to a generic library of built-in logic gates and registers.
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The built-in logic gate types are: ``$_NOT_``, ``$_AND_``, ``$_OR_``,
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``$_XOR_``, and ``$_MUX_``.
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The register types are: ``$_SR_NN_``, ``$_SR_NP_``, ``$_SR_PN_``, ``$_SR_PP_``,
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``$_DFF_N_``, ``$_DFF_P_ $_DFF_NN0_``, ``$_DFF_NN1_``, ``$_DFF_NP0_``,
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``$_DFF_NP1_``, ``$_DFF_PN0_``, ``$_DFF_PN1_``, ``$_DFF_PP0_ $_DFF_PP1_``,
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``$_DFFSR_NNN_``, ``$_DFFSR_NNP_``, ``$_DFFSR_NPN_``, ``$_DFFSR_NPP_``,
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``$_DFFSR_PNN_ $_DFFSR_PNP_``, ``$_DFFSR_PPN_``, ``$_DFFSR_PPP_``,
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``$_DLATCH_N_``, and ``$_DLATCH_P_``.
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See :doc:`/yosys_internals/formats/cell_library` for more about the internal
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cells used.
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The ``abc`` command
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~~~~~~~~~~~~~~~~~~~~~
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The ``abc`` command provides an interface to ABC_, an open source tool for
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low-level logic synthesis.
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.. _ABC: http://www.eecs.berkeley.edu/~alanmi/abc/
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The ``abc`` command processes a netlist of internal gate types and can perform:
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- logic minimization (optimization)
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- mapping of logic to standard cell library (liberty format)
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- mapping of logic to k-LUTs (for FPGA synthesis)
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Optionally ``abc`` can process registers from one clock domain and perform
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sequential optimization (such as register balancing).
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ABC is also controlled using scripts. An ABC script can be specified to use more
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advanced ABC features. It is also possible to write the design with
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``write_blif`` and load the output file into ABC outside of Yosys.
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Example
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^^^^^^^
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.. literalinclude:: ../../resources/PRESENTATION_ExSyn/abc_01.v
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:language: verilog
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:caption: ``docs/resources/PRESENTATION_ExSyn/abc_01.v``
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.. literalinclude:: ../../resources/PRESENTATION_ExSyn/abc_01.ys
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:language: yoscrypt
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:caption: ``docs/resources/PRESENTATION_ExSyn/abc_01.ys``
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.. figure:: ../../images/res/PRESENTATION_ExSyn/abc_01.*
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:class: width-helper
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Other special-purpose mapping commands
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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``dfflibmap``
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This command maps the internal register cell types to the register types
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described in a liberty file.
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``hilomap``
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Some architectures require special driver cells for driving a constant hi or
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lo value. This command replaces simple constants with instances of such driver
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cells.
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``iopadmap``
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Top-level input/outputs must usually be implemented using special I/O-pad
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cells. This command inserts this cells to the design.
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Example Synthesis Script
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~~~~~~~~~~~~~~~~~~~~~~~~
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.. code-block:: yoscrypt
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# read and elaborate design
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read_verilog cpu_top.v cpu_ctrl.v cpu_regs.v
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read_verilog -D WITH_MULT cpu_alu.v
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hierarchy -check -top cpu_top
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# high-level synthesis
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proc; opt; fsm;; memory -nomap; opt
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# substitute block rams
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techmap -map map_rams.v
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# map remaining memories
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memory_map
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# low-level synthesis
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techmap; opt; flatten;; abc -lut6
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techmap -map map_xl_cells.v
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# add clock buffers
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select -set xl_clocks t:FDRE %x:+FDRE[C] t:FDRE %d
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iopadmap -inpad BUFGP O:I @xl_clocks
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# add io buffers
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select -set xl_nonclocks w:* t:BUFGP %x:+BUFGP[I] %d
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iopadmap -outpad OBUF I:O -inpad IBUF O:I @xl_nonclocks
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# write synthesis results
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write_edif synth.edif
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The weird ``select`` expressions at the end of this script are discussed later
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in :doc:`using_yosys/more_scripting/selections</using_yosys/more_scripting/selections>`.
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