mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-28 19:35:53 +00:00
Code Activity

Converting PRESENTATION_ExSyn

Browse source
This commit is contained in:
Krystine Sherwin 2023-08-04 10:29:14 +12:00
parent 4b40372446
commit 330a2272da
No known key found for this signature in database
31 changed files with 442 additions and 517 deletions
Download patch file Download diff file Expand all files Collapse all files

10
docs/resources/PRESENTATION_ExSyn/proc_03.v Normal file
View file

@ -0,0 +1,10 @@
module test(input A, B, C, D, E,
output reg Y);
always @* begin
Y <= A;
if (B)
Y <= C;
if (D)
Y <= E;
end
endmodule