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Converting PRESENTATION_ExSyn

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Krystine Sherwin 2023-08-04 10:29:14 +12:00
parent 4b40372446
commit 330a2272da
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31 changed files with 442 additions and 517 deletions
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8
docs/resources/PRESENTATION_ExSyn/proc_02.v Normal file
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@ -0,0 +1,8 @@
module test(input D, C, R, RV,
output reg Q);
always @(posedge C, posedge R)
if (R)
Q <= RV;
else
Q <= D;
endmodule