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Converting PRESENTATION_ExSyn

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This commit is contained in:
Krystine Sherwin 2023-08-04 10:29:14 +12:00
parent 4b40372446
commit 330a2272da
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31 changed files with 442 additions and 517 deletions
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19
docs/resources/PRESENTATION_ExSyn/opt_04.v Normal file
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@ -0,0 +1,19 @@
module test(input CLK, ARST,
output [7:0] Q1, Q2, Q3);
wire NO_CLK = 0;
always @(posedge CLK, posedge ARST)
if (ARST)
Q1 <= 42;
always @(posedge NO_CLK, posedge ARST)
if (ARST)
Q2 <= 42;
else
Q2 <= 23;
always @(posedge CLK)
Q3 <= 42;
endmodule