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Converting PRESENTATION_ExSyn

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Krystine Sherwin 2023-08-04 10:29:14 +12:00
parent 4b40372446
commit 330a2272da
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31 changed files with 442 additions and 517 deletions
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docs/resources/PRESENTATION_ExSyn/memory_02.ys Normal file
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@ -0,0 +1,4 @@
read_verilog memory_02.v
hierarchy -check -top test
proc;; memory -nomap
opt -mux_undef -mux_bool