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Converting PRESENTATION_ExSyn

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Krystine Sherwin 2023-08-04 10:29:14 +12:00
parent 4b40372446
commit 330a2272da
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31 changed files with 442 additions and 517 deletions
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10
docs/resources/PRESENTATION_ExSyn/abc_01.v Normal file
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@ -0,0 +1,10 @@
module test(input clk, a, b, c,
output reg y);
reg [2:0] q1, q2;
always @(posedge clk) begin
q1 <= { a, b, c };
q2 <= q1;
y <= ^q2;
end
endmodule