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Add more tests
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@ -187,7 +187,6 @@ module case_nonexclusive_select (
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);
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);
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always @* begin
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always @* begin
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case (x)
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case (x)
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//0, 2: o = b;
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0: o = b;
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0: o = b;
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2: o = b;
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2: o = b;
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1: o = c;
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1: o = c;
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@ -202,22 +201,16 @@ endmodule
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module case_nonoverlap (
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module case_nonoverlap (
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input wire [2:0] x,
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input wire [2:0] x,
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input wire a, b, c, d, e, f, g,
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input wire a, b, c, d, e,
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output reg o
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output reg o
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);
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);
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always @* begin
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always @* begin
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case (x)
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case (x)
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//0, 2: o = b; // Creates $reduce_or
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0, 2: o = b; // Creates $reduce_or
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//0: o = b; 2: o = b; // Creates $reduce_or
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0: o = b;
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2: o = f;
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1: o = c;
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1: o = c;
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default:
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default:
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case (x)
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case (x)
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//3, 4: o = d; // Creates $reduce_or
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3: o = d; 4: o = d; // Creates $reduce_or
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//3: o = d; 4: o = d; // Creates $reduce_or
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3: o = d;
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4: o = g;
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5: o = e;
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5: o = e;
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default: o = 1'b0;
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default: o = 1'b0;
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endcase
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endcase
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@ -227,23 +220,37 @@ endmodule
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module case_overlap (
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module case_overlap (
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input wire [2:0] x,
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input wire [2:0] x,
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input wire a, b, c, d, e, f, g,
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input wire a, b, c, d, e,
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output reg o
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output reg o
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);
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);
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always @* begin
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always @* begin
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case (x)
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case (x)
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//0, 2: o = b; // Creates $reduce_or
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0, 2: o = b; // Creates $reduce_or
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//0: o = b; 2: o = b; // Creates $reduce_or
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0: o = b;
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2: o = f;
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1: o = c;
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1: o = c;
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default:
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default:
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case (x)
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case (x)
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//3, 4: o = d; // Creates $reduce_or
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0: o = 1'b1; // OVERLAP!
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//3: o = d; 4: o = d; // Creates $reduce_or
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3, 4: o = d; // Creates $reduce_or
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2: o = 1'b1; // Overlaps with previous $pmux
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5: o = e;
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3: o = d;
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default: o = 1'b0;
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4: o = g;
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endcase
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endcase
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end
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endmodule
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module case_overlap2 (
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input wire [2:0] x,
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input wire a, b, c, d, e,
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output reg o
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);
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always @* begin
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case (x)
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0: o = b; 2: o = b; // Creates $reduce_or
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1: o = c;
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default:
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case (x)
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0: o = d; 2: o = d; // Creates $reduce_or
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3: o = d; 4: o = d; // Creates $reduce_or
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5: o = e;
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5: o = e;
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default: o = 1'b0;
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default: o = 1'b0;
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endcase
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endcase
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@ -215,8 +215,11 @@ sat -verify -prove-asserts -show-ports miter
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design -load read
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design -load read
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hierarchy -top case_nonoverlap
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hierarchy -top case_nonoverlap
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prep
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#prep # Do not prep otherwise $pmux's overlapping entry will get removed
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proc
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design -save gold
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design -save gold
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opt -fast -mux_undef
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select -assert-count 2 t:$pmux
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muxpack
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muxpack
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opt
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opt
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stat
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stat
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@ -233,6 +236,26 @@ hierarchy -top case_overlap
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#prep # Do not prep otherwise $pmux's overlapping entry will get removed
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#prep # Do not prep otherwise $pmux's overlapping entry will get removed
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proc
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proc
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design -save gold
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design -save gold
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opt -fast -mux_undef
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select -assert-count 2 t:$pmux
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muxpack
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opt
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stat
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select -assert-count 0 t:$mux
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select -assert-count 2 t:$pmux
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design -stash gate
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design -import gold -as gold
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design -import gate -as gate
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miter -equiv -flatten -make_assert -make_outputs gold gate miter
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sat -verify -prove-asserts -show-ports miter
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design -load read
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hierarchy -top case_overlap2
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#prep # Do not prep otherwise $pmux's overlapping entry will get removed
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proc
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design -save gold
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opt -fast -mux_undef
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select -assert-count 2 t:$pmux
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muxpack
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muxpack
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opt
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opt
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stat
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stat
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