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Fixed clock related parameter names for $memrd and $memwr in techlibs/simlib.v

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This commit is contained in:
Clifford Wolf 2013-04-07 16:42:29 +02:00
parent af4444e5b9
commit 32dbf7752d
1 changed files with 4 additions and 4 deletions
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8
techlibs/simlib.v
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@ -799,8 +799,8 @@ parameter MEMID = "";
parameter ABITS = 8;
parameter WIDTH = 8;
parameter RD_CLK_ENABLE = 0;
parameter RD_CLK_POLARITY = 0;
parameter CLK_ENABLE = 0;
parameter CLK_POLARITY = 0;
input CLK;
input [ABITS-1:0] ADDR;
@ -821,8 +821,8 @@ parameter MEMID = "";
parameter ABITS = 8;
parameter WIDTH = 8;
parameter RD_CLK_ENABLE = 0;
parameter RD_CLK_POLARITY = 0;
parameter CLK_ENABLE = 0;
parameter CLK_POLARITY = 0;
input CLK, EN;
input [ABITS-1:0] ADDR;