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Add support for source line tracking through synthesis phase

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This commit is contained in:
Jason Lowdermilk 2017-08-29 14:46:35 -06:00
parent 393b18e8e1
commit 32c0f1193e
5 changed files with 45 additions and 25 deletions
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4
passes/techmap/dfflibmap.cc
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@ -478,11 +478,15 @@ static void dfflibmap(RTLIL::Design *design, RTLIL::Module *module, bool prepare
auto cell_type = cell->type;
auto cell_name = cell->name;
auto cell_connections = cell->connections();
std::string src = cell->attributes["\\src"].decode_string();
module->remove(cell);
cell_mapping &cm = cell_mappings[cell_type];
RTLIL::Cell *new_cell = module->addCell(cell_name, prepare_mode ? cm.cell_name : "\\" + cm.cell_name);
if (!src.empty()) new_cell->attributes["\\src"] = src;
bool has_q = false, has_qn = false;
for (auto &port : cm.ports) {
if (port.second == 'Q') has_q = true;