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Added examples/anlogic/

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Kali Prasad 2019-03-04 23:26:56 +05:30
parent 107d884804
commit 32a901ddf2
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18
examples/anlogic/demo.v Normal file
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module demo (
input wire CLK_IN,
output wire R_LED
);
parameter time1 = 30'd12_000_000;
reg led_state;
reg [29:0] count;
always @(posedge CLK_IN)begin
if(count == time1)begin
count<= 30'd0;
led_state <= ~led_state;
end
else
count <= count + 1'b1;
end
assign R_LED = led_state;
endmodule