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Fix "a" extension
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parent
01684643b6
commit
32a4c10c0d
2 changed files with 21 additions and 9 deletions
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@ -681,9 +681,12 @@ struct XAigerWriter
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for (auto cell : box_list) {
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RTLIL::Module* box_module = module->design->module(cell->type);
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int box_inputs = 0, box_outputs = 0;
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Cell *holes_cell = holes_module->addCell(cell->name, cell->type);
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Cell *holes_cell = nullptr;
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if (box_module->get_bool_attribute("\\whitebox"))
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holes_cell = holes_module->addCell(cell->name, cell->type);
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RTLIL::Wire *holes_wire;
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// TODO: Only sort once
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box_module->wires_.sort(RTLIL::sort_by_id_str());
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for (const auto w : box_module->wires()) {
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RTLIL::SigSpec port_wire;
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@ -695,9 +698,11 @@ struct XAigerWriter
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holes_wire = holes_module->addWire(stringf("\\i%d", box_inputs));
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holes_wire->port_input = true;
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}
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port_wire.append(holes_wire);
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if (holes_cell)
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port_wire.append(holes_wire);
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}
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holes_cell->setPort(w->name, port_wire);
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if (!port_wire.empty())
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holes_cell->setPort(w->name, port_wire);
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}
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if (w->port_output) {
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box_outputs += GetSize(w);
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@ -707,9 +712,13 @@ struct XAigerWriter
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else
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holes_wire = holes_module->addWire(stringf("%s.%s[%d]", cell->name.c_str(), w->name.c_str(), i));
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holes_wire->port_output = true;
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port_wire.append(holes_wire);
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if (holes_cell)
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port_wire.append(holes_wire);
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else
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holes_module->connect(holes_wire, RTLIL::S0);
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}
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holes_cell->setPort(w->name, port_wire);
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if (!port_wire.empty())
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holes_cell->setPort(w->name, port_wire);
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}
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}
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@ -741,12 +750,13 @@ struct XAigerWriter
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// each box type once...
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Pass::call(holes_module->design, "opt_merge -share_all");
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Pass::call(holes_module->design, "flatten -wb;");
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Pass::call(holes_module->design, "flatten -wb");
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// TODO: Should techmap all lib_whitebox-es once
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Pass::call(holes_module->design, "techmap;");
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//Pass::call(holes_module->design, "techmap");
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Pass::call(holes_module->design, "aigmap; clean -purge");
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Pass::call(holes_module->design, "aigmap");
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Pass::call(holes_module->design, "clean -purge");
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holes_module->design->selection_stack.pop_back();
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