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Emit errors before dfflegalize.

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This commit is contained in:
nella 2026-06-18 17:07:24 +02:00
parent b2d688dbf9
commit 32a268d745
10 changed files with 81 additions and 28 deletions
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2
docs/source/code_examples/macro_commands/synth_ice40.ys
View file

@ -67,7 +67,7 @@ map_ffs:
map_luts: map_luts:
abc abc
ice40_opt ice40_opt
select check
techmap techmap
simplemap simplemap
techmap techmap

22
passes/cmds/check.cc
View file

@ -124,12 +124,27 @@ struct CheckPass : public Pass {
} }
extra_args(args, argidx, design); extra_args(args, argidx, design);
bool latchonly = design->scratchpad_get_bool("check.latchonly", false);
log_header(design, "Executing CHECK pass (checking for obvious problems).\n"); log_header(design, "Executing CHECK pass (checking for obvious problems).\n");
for (auto module : design->selected_whole_modules_warn()) for (auto module : design->selected_whole_modules_warn())
{ {
log("Checking module %s...\n", module); log("Checking module %s...\n", module);
// latch-only mode only flags latches, skipping the (potentially false-positive mid-flow) undriven/driver/loop checks below
if (latchonly) {
for (auto cell : module->cells())
if (
cell->type.in(ID($dlatch), ID($adlatch), ID($dlatchsr)) ||
cell->type.begins_with("$_DLATCH_") || cell->type.begins_with("$_DLATCHSR_")
) {
log_warning("Cell %s.%s is a latch of type %s.\n", module, cell, cell->type.unescape());
counter++;
}
continue;
}
SigMap sigmap(module); SigMap sigmap(module);
dict<SigBit, vector<string>> wire_drivers; dict<SigBit, vector<string>> wire_drivers;
dict<SigBit, Cell *> driver_cells; dict<SigBit, Cell *> driver_cells;
@ -275,8 +290,11 @@ struct CheckPass : public Pass {
cell_allowed:; cell_allowed:;
} }
if (nolatches && (cell->type.in(ID($dlatch), ID($adlatch), ID($dlatchsr)) || if (
cell->type.begins_with("$_DLATCH_") || cell->type.begins_with("$_DLATCHSR_"))) { nolatches && (
cell->type.in(ID($dlatch), ID($adlatch), ID($dlatchsr)) ||
cell->type.begins_with("$_DLATCH_") || cell->type.begins_with("$_DLATCHSR_"))
) {
log_warning("Cell %s.%s is a latch of type %s.\n", module, cell, cell->type.unescape()); log_warning("Cell %s.%s is a latch of type %s.\n", module, cell, cell->type.unescape());
counter++; counter++;
} }

11
techlibs/efinix/synth_efinix.cc
View file

@ -160,7 +160,7 @@ struct SynthEfinixPass : public ScriptPass
if (flatten && check_label("flatten", "(unless -noflatten)")) if (flatten && check_label("flatten", "(unless -noflatten)"))
{ {
run("proc -latches " + (latches == "error" ? std::string("auto") : latches)); run("proc -latches " + (latches == "auto" ? std::string("auto") : std::string("warn")));
run("check"); run("check");
run("flatten"); run("flatten");
run("tribuf -logic"); run("tribuf -logic");
@ -204,9 +204,12 @@ struct SynthEfinixPass : public ScriptPass
{ {
run("dfflegalize -cell $_DFFE_????_ 0 -cell $_SDFFE_????_ 0 -cell $_SDFFCE_????_ 0 -cell $_DLATCH_?_ x"); run("dfflegalize -cell $_DFFE_????_ 0 -cell $_SDFFE_????_ 0 -cell $_SDFFCE_????_ 0 -cell $_DLATCH_?_ x");
if (help_mode) if (help_mode)
run("select -assert-none t:$_DLATCH_* t:$_DLATCHSR_*", "(only if -latches error, the default)"); run("check -assert", "(only if -latches error, the default)");
else if (latches == "error") else if (latches == "error") {
run("select -assert-none t:$_DLATCH_* t:$_DLATCHSR_*"); active_design->scratchpad_set_bool("check.latchonly", true);
run("check -assert");
active_design->scratchpad_unset("check.latchonly");
}
run("techmap -D NO_LUT -map +/efinix/cells_map.v"); run("techmap -D NO_LUT -map +/efinix/cells_map.v");
run("opt_expr -mux_undef"); run("opt_expr -mux_undef");
run("simplemap"); run("simplemap");

11
techlibs/fabulous/synth_fabulous.cc
View file

@ -292,7 +292,7 @@ struct SynthPass : public ScriptPass
run("hierarchy -check"); run("hierarchy -check");
} else } else
run(stringf("hierarchy -check -top %s", top_module)); run(stringf("hierarchy -check -top %s", top_module));
run("proc -latches " + (latches == "error" ? std::string("auto") : latches)); run("proc -latches " + (latches == "auto" ? std::string("auto") : std::string("warn")));
} }
@ -373,9 +373,12 @@ struct SynthPass : public ScriptPass
run("dfflegalize -cell $_DFF_P_ 0 -cell $_DLATCH_?_ x", "without -complex-dff"); run("dfflegalize -cell $_DFF_P_ 0 -cell $_DLATCH_?_ x", "without -complex-dff");
} }
if (help_mode) if (help_mode)
run("select -assert-none t:$_DLATCH_* t:$_DLATCHSR_*", "(only if -latches error, the default)"); run("check -assert", "(only if -latches error, the default)");
else if (latches == "error") else if (latches == "error") {
run("select -assert-none t:$_DLATCH_* t:$_DLATCHSR_*"); active_design->scratchpad_set_bool("check.latchonly", true);
run("check -assert");
active_design->scratchpad_unset("check.latchonly");
}
run("techmap -map +/fabulous/latches_map.v"); run("techmap -map +/fabulous/latches_map.v");
run("techmap -map +/fabulous/ff_map.v"); run("techmap -map +/fabulous/ff_map.v");
if (help_mode) { if (help_mode) {

11
techlibs/ice40/synth_ice40.cc
View file

@ -316,7 +316,7 @@ struct SynthIce40Pass : public ScriptPass
{ {
run("read_verilog " + define + " -lib -specify +/ice40/cells_sim.v"); run("read_verilog " + define + " -lib -specify +/ice40/cells_sim.v");
run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt)); run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt));
run("proc -latches " + (latches == "error" ? std::string("auto") : latches)); run("proc -latches " + (latches == "auto" ? std::string("auto") : std::string("warn")));
} }
if (check_label("flatten", "(unless -noflatten)")) if (check_label("flatten", "(unless -noflatten)"))
@ -420,9 +420,12 @@ struct SynthIce40Pass : public ScriptPass
run("ice40_opt", "(only if -abc2)"); run("ice40_opt", "(only if -abc2)");
} }
if (help_mode) if (help_mode)
run("select -assert-none t:$_DLATCH_* t:$_DLATCHSR_*", "(only if -latches error, the default)"); run("check -assert", "(only if -latches error, the default)");
else if (latches == "error") else if (latches == "error") {
run("select -assert-none t:$_DLATCH_* t:$_DLATCHSR_*"); active_design->scratchpad_set_bool("check.latchonly", true);
run("check -assert");
active_design->scratchpad_unset("check.latchonly");
}
run("techmap -map +/ice40/latches_map.v"); run("techmap -map +/ice40/latches_map.v");
if (noabc || flowmap || help_mode) { if (noabc || flowmap || help_mode) {
run("simplemap", " (if -noabc or -flowmap)"); run("simplemap", " (if -noabc or -flowmap)");

11
techlibs/lattice/synth_lattice.cc
View file

@ -416,7 +416,7 @@ struct SynthLatticePass : public ScriptPass
if (check_label("coarse")) if (check_label("coarse"))
{ {
run("proc -latches " + ((asyncprld || latches == "error") ? std::string("auto") : latches)); run("proc -latches " + ((asyncprld || latches == "auto") ? std::string("auto") : std::string("warn")));
if (flatten || help_mode) { if (flatten || help_mode) {
run("check"); run("check");
run("flatten"); run("flatten");
@ -548,9 +548,12 @@ struct SynthLatticePass : public ScriptPass
run("abc", " (only if -abc2)"); run("abc", " (only if -abc2)");
if (!asyncprld || help_mode) { if (!asyncprld || help_mode) {
if (help_mode) if (help_mode)
run("select -assert-none t:$_DLATCH_* t:$_DLATCHSR_*", "(skip if -asyncprld; only if -latches error, the default)"); run("check -assert", "(skip if -asyncprld; only if -latches error, the default)");
else if (latches == "error") else if (latches == "error") {
run("select -assert-none t:$_DLATCH_* t:$_DLATCHSR_*"); active_design->scratchpad_set_bool("check.latchonly", true);
run("check -assert");
active_design->scratchpad_unset("check.latchonly");
}
run("techmap -map +/lattice/latches_map.v", "(skip if -asyncprld)"); run("techmap -map +/lattice/latches_map.v", "(skip if -asyncprld)");
} }

11
techlibs/nanoxplore/synth_nanoxplore.cc
View file

@ -263,7 +263,7 @@ struct SynthNanoXplorePass : public ScriptPass
if (check_label("coarse")) if (check_label("coarse"))
{ {
run("proc -latches " + (latches == "error" ? std::string("auto") : latches)); run("proc -latches " + (latches == "auto" ? std::string("auto") : std::string("warn")));
if (flatten || help_mode) { if (flatten || help_mode) {
run("check"); run("check");
run("flatten", "(skip if -noflatten)"); run("flatten", "(skip if -noflatten)");
@ -340,9 +340,12 @@ struct SynthNanoXplorePass : public ScriptPass
run("dfflegalize" + dfflegalize_args,"($_*DFFE_* only if not -nodffe)"); run("dfflegalize" + dfflegalize_args,"($_*DFFE_* only if not -nodffe)");
run("opt_merge"); run("opt_merge");
if (help_mode) if (help_mode)
run("select -assert-none t:$_DLATCH_* t:$_DLATCHSR_*", "(only if -latches error, the default)"); run("check -assert", "(only if -latches error, the default)");
else if (latches == "error") else if (latches == "error") {
run("select -assert-none t:$_DLATCH_* t:$_DLATCHSR_*"); active_design->scratchpad_set_bool("check.latchonly", true);
run("check -assert");
active_design->scratchpad_unset("check.latchonly");
}
run("techmap -map +/nanoxplore/latches_map.v"); run("techmap -map +/nanoxplore/latches_map.v");
run("techmap -map +/nanoxplore/cells_map.v"); run("techmap -map +/nanoxplore/cells_map.v");
run("opt_expr -undriven -mux_undef"); run("opt_expr -undriven -mux_undef");

11
techlibs/quicklogic/synth_quicklogic.cc
View file

@ -226,7 +226,7 @@ struct SynthQuickLogicPass : public ScriptPass {
} }
if (check_label("prepare")) { if (check_label("prepare")) {
run("proc -latches " + ((family == "pp3" && latches != "error") ? latches : std::string("auto"))); run("proc -latches " + ((family == "pp3" && latches != "auto") ? std::string("warn") : std::string("auto")));
if (flatten) { if (flatten) {
run("check"); run("check");
run("flatten", "(unless -noflatten)"); run("flatten", "(unless -noflatten)");
@ -331,9 +331,12 @@ struct SynthQuickLogicPass : public ScriptPass {
if (check_label("map_luts", "(for pp3)") && (help_mode || family == "pp3")) { if (check_label("map_luts", "(for pp3)") && (help_mode || family == "pp3")) {
if (help_mode) if (help_mode)
run("select -assert-none t:$_DLATCH_* t:$_DLATCHSR_*", "(only if -latches error, the default)"); run("check -assert", "(only if -latches error, the default)");
else if (latches == "error") else if (latches == "error") {
run("select -assert-none t:$_DLATCH_* t:$_DLATCHSR_*"); active_design->scratchpad_set_bool("check.latchonly", true);
run("check -assert");
active_design->scratchpad_unset("check.latchonly");
}
run("techmap -map " + lib_path + family + "/latches_map.v"); run("techmap -map " + lib_path + family + "/latches_map.v");
if (abc9) { if (abc9) {
run("read_verilog -lib -specify -icells " + lib_path + family + "/abc9_model.v"); run("read_verilog -lib -specify -icells " + lib_path + family + "/abc9_model.v");

16
tests/various/check_nolatches.ys
View file

@ -29,3 +29,19 @@ EOT
proc proc
logger -expect error "Found 1 problems in" 1 logger -expect error "Found 1 problems in" 1
check -nolatches -assert check -nolatches -assert
design -reset
read_verilog <<EOT
module top(input g, d, output reg q, output y);
always @* if (g) q = d;
wire u;
assign y = u;
endmodule
EOT
proc
scratchpad -set check.latchonly 1
logger -expect warning "is a latch of type" 1
logger -expect warning "used but has no driver" 0
logger -expect error "Found 1 problems in" 1
check -assert

3
tests/various/synth_latch_warning.ys
View file

@ -15,5 +15,6 @@ synth_ice40 -latches auto
select -assert-count 1 t:SB_LUT4 select -assert-count 1 t:SB_LUT4
design -load read design -load read
logger -expect error "selection is not empty: t:._DLATCH_" 1 logger -expect warning "Latch inferred for signal" 1
logger -expect error "Found 1 problems in 'check -assert'" 1
synth_ice40 synth_ice40