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Emit errors before dfflegalize.

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This commit is contained in:
nella 2026-06-18 17:07:24 +02:00
parent b2d688dbf9
commit 32a268d745
10 changed files with 81 additions and 28 deletions
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11
techlibs/efinix/synth_efinix.cc
View file

@ -160,7 +160,7 @@ struct SynthEfinixPass : public ScriptPass
if (flatten && check_label("flatten", "(unless -noflatten)"))
{
run("proc -latches " + (latches == "error" ? std::string("auto") : latches));
run("proc -latches " + (latches == "auto" ? std::string("auto") : std::string("warn")));
run("check");
run("flatten");
run("tribuf -logic");
@ -204,9 +204,12 @@ struct SynthEfinixPass : public ScriptPass
{
run("dfflegalize -cell $_DFFE_????_ 0 -cell $_SDFFE_????_ 0 -cell $_SDFFCE_????_ 0 -cell $_DLATCH_?_ x");
if (help_mode)
run("select -assert-none t:$_DLATCH_* t:$_DLATCHSR_*", "(only if -latches error, the default)");
else if (latches == "error")
run("select -assert-none t:$_DLATCH_* t:$_DLATCHSR_*");
run("check -assert", "(only if -latches error, the default)");
else if (latches == "error") {
active_design->scratchpad_set_bool("check.latchonly", true);
run("check -assert");
active_design->scratchpad_unset("check.latchonly");
}
run("techmap -D NO_LUT -map +/efinix/cells_map.v");
run("opt_expr -mux_undef");
run("simplemap");

11
techlibs/fabulous/synth_fabulous.cc
View file

@ -292,7 +292,7 @@ struct SynthPass : public ScriptPass
run("hierarchy -check");
} else
run(stringf("hierarchy -check -top %s", top_module));
run("proc -latches " + (latches == "error" ? std::string("auto") : latches));
run("proc -latches " + (latches == "auto" ? std::string("auto") : std::string("warn")));
}
@ -373,9 +373,12 @@ struct SynthPass : public ScriptPass
run("dfflegalize -cell $_DFF_P_ 0 -cell $_DLATCH_?_ x", "without -complex-dff");
}
if (help_mode)
run("select -assert-none t:$_DLATCH_* t:$_DLATCHSR_*", "(only if -latches error, the default)");
else if (latches == "error")
run("select -assert-none t:$_DLATCH_* t:$_DLATCHSR_*");
run("check -assert", "(only if -latches error, the default)");
else if (latches == "error") {
active_design->scratchpad_set_bool("check.latchonly", true);
run("check -assert");
active_design->scratchpad_unset("check.latchonly");
}
run("techmap -map +/fabulous/latches_map.v");
run("techmap -map +/fabulous/ff_map.v");
if (help_mode) {

11
techlibs/ice40/synth_ice40.cc
View file

@ -316,7 +316,7 @@ struct SynthIce40Pass : public ScriptPass
{
run("read_verilog " + define + " -lib -specify +/ice40/cells_sim.v");
run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt));
run("proc -latches " + (latches == "error" ? std::string("auto") : latches));
run("proc -latches " + (latches == "auto" ? std::string("auto") : std::string("warn")));
}
if (check_label("flatten", "(unless -noflatten)"))
@ -420,9 +420,12 @@ struct SynthIce40Pass : public ScriptPass
run("ice40_opt", "(only if -abc2)");
}
if (help_mode)
run("select -assert-none t:$_DLATCH_* t:$_DLATCHSR_*", "(only if -latches error, the default)");
else if (latches == "error")
run("select -assert-none t:$_DLATCH_* t:$_DLATCHSR_*");
run("check -assert", "(only if -latches error, the default)");
else if (latches == "error") {
active_design->scratchpad_set_bool("check.latchonly", true);
run("check -assert");
active_design->scratchpad_unset("check.latchonly");
}
run("techmap -map +/ice40/latches_map.v");
if (noabc || flowmap || help_mode) {
run("simplemap", " (if -noabc or -flowmap)");

11
techlibs/lattice/synth_lattice.cc
View file

@ -416,7 +416,7 @@ struct SynthLatticePass : public ScriptPass
if (check_label("coarse"))
{
run("proc -latches " + ((asyncprld || latches == "error") ? std::string("auto") : latches));
run("proc -latches " + ((asyncprld || latches == "auto") ? std::string("auto") : std::string("warn")));
if (flatten || help_mode) {
run("check");
run("flatten");
@ -548,9 +548,12 @@ struct SynthLatticePass : public ScriptPass
run("abc", " (only if -abc2)");
if (!asyncprld || help_mode) {
if (help_mode)
run("select -assert-none t:$_DLATCH_* t:$_DLATCHSR_*", "(skip if -asyncprld; only if -latches error, the default)");
else if (latches == "error")
run("select -assert-none t:$_DLATCH_* t:$_DLATCHSR_*");
run("check -assert", "(skip if -asyncprld; only if -latches error, the default)");
else if (latches == "error") {
active_design->scratchpad_set_bool("check.latchonly", true);
run("check -assert");
active_design->scratchpad_unset("check.latchonly");
}
run("techmap -map +/lattice/latches_map.v", "(skip if -asyncprld)");
}

11
techlibs/nanoxplore/synth_nanoxplore.cc
View file

@ -263,7 +263,7 @@ struct SynthNanoXplorePass : public ScriptPass
if (check_label("coarse"))
{
run("proc -latches " + (latches == "error" ? std::string("auto") : latches));
run("proc -latches " + (latches == "auto" ? std::string("auto") : std::string("warn")));
if (flatten || help_mode) {
run("check");
run("flatten", "(skip if -noflatten)");
@ -340,9 +340,12 @@ struct SynthNanoXplorePass : public ScriptPass
run("dfflegalize" + dfflegalize_args,"($_*DFFE_* only if not -nodffe)");
run("opt_merge");
if (help_mode)
run("select -assert-none t:$_DLATCH_* t:$_DLATCHSR_*", "(only if -latches error, the default)");
else if (latches == "error")
run("select -assert-none t:$_DLATCH_* t:$_DLATCHSR_*");
run("check -assert", "(only if -latches error, the default)");
else if (latches == "error") {
active_design->scratchpad_set_bool("check.latchonly", true);
run("check -assert");
active_design->scratchpad_unset("check.latchonly");
}
run("techmap -map +/nanoxplore/latches_map.v");
run("techmap -map +/nanoxplore/cells_map.v");
run("opt_expr -undriven -mux_undef");

11
techlibs/quicklogic/synth_quicklogic.cc
View file

@ -226,7 +226,7 @@ struct SynthQuickLogicPass : public ScriptPass {
}
if (check_label("prepare")) {
run("proc -latches " + ((family == "pp3" && latches != "error") ? latches : std::string("auto")));
run("proc -latches " + ((family == "pp3" && latches != "auto") ? std::string("warn") : std::string("auto")));
if (flatten) {
run("check");
run("flatten", "(unless -noflatten)");
@ -331,9 +331,12 @@ struct SynthQuickLogicPass : public ScriptPass {
if (check_label("map_luts", "(for pp3)") && (help_mode || family == "pp3")) {
if (help_mode)
run("select -assert-none t:$_DLATCH_* t:$_DLATCHSR_*", "(only if -latches error, the default)");
else if (latches == "error")
run("select -assert-none t:$_DLATCH_* t:$_DLATCHSR_*");
run("check -assert", "(only if -latches error, the default)");
else if (latches == "error") {
active_design->scratchpad_set_bool("check.latchonly", true);
run("check -assert");
active_design->scratchpad_unset("check.latchonly");
}
run("techmap -map " + lib_path + family + "/latches_map.v");
if (abc9) {
run("read_verilog -lib -specify -icells " + lib_path + family + "/abc9_model.v");