mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2026-06-26 10:38:47 +00:00
Code Activity

Emit errors before dfflegalize.

Browse source
This commit is contained in:
nella 2026-06-18 17:07:24 +02:00
parent b2d688dbf9
commit 32a268d745
10 changed files with 81 additions and 28 deletions
Download patch file Download diff file Expand all files Collapse all files

22
passes/cmds/check.cc
View file

@ -124,12 +124,27 @@ struct CheckPass : public Pass {
}
extra_args(args, argidx, design);
bool latchonly = design->scratchpad_get_bool("check.latchonly", false);
log_header(design, "Executing CHECK pass (checking for obvious problems).\n");
for (auto module : design->selected_whole_modules_warn())
{
log("Checking module %s...\n", module);
// latch-only mode only flags latches, skipping the (potentially false-positive mid-flow) undriven/driver/loop checks below
if (latchonly) {
for (auto cell : module->cells())
if (
cell->type.in(ID($dlatch), ID($adlatch), ID($dlatchsr)) ||
cell->type.begins_with("$_DLATCH_") || cell->type.begins_with("$_DLATCHSR_")
) {
log_warning("Cell %s.%s is a latch of type %s.\n", module, cell, cell->type.unescape());
counter++;
}
continue;
}
SigMap sigmap(module);
dict<SigBit, vector<string>> wire_drivers;
dict<SigBit, Cell *> driver_cells;
@ -275,8 +290,11 @@ struct CheckPass : public Pass {
cell_allowed:;
}
if (nolatches && (cell->type.in(ID($dlatch), ID($adlatch), ID($dlatchsr)) ||
cell->type.begins_with("$_DLATCH_") || cell->type.begins_with("$_DLATCHSR_"))) {
if (
nolatches && (
cell->type.in(ID($dlatch), ID($adlatch), ID($dlatchsr)) ||
cell->type.begins_with("$_DLATCH_") || cell->type.begins_with("$_DLATCHSR_"))
) {
log_warning("Cell %s.%s is a latch of type %s.\n", module, cell, cell->type.unescape());
counter++;
}