mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-10-31 03:32:29 +00:00
Code Activity

quicklogic: ql_dsp_simd add dspv1 test

Browse source
This commit is contained in:
Emil J. Tywoniak 2025-03-06 12:56:11 +01:00 • committed by Martin Povišer
parent 281669667c
commit 329e6b366e
1 changed files with 63 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

63
tests/arch/quicklogic/qlf_k6n10f/dspv1_simd.ys Normal file
View file

@ -0,0 +1,63 @@
read_verilog <<EOT
module foo(
input [7:0] A,
input [7:0] B,
input [7:0] C,
input [7:0] D,
output reg [7:0] X,
output reg [7:0] Y);
assign X = A * B;
assign Y = C * D;
endmodule
EOT
synth_quicklogic -run :map_dsp
# this is just taken from map_dsp step
wreduce t:$mul
ql_dsp_macc
techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=20 -D DSP_B_MAXWIDTH=18 -D DSP_A_MINWIDTH=11 -D DSP_B_MINWIDTH=10 -D DSP_NAME=$__QL_MUL20X18
chtype -set $mul t:$__soft_mul
techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=10 -D DSP_B_MAXWIDTH=9 -D DSP_A_MINWIDTH=4 -D DSP_B_MINWIDTH=4 -D DSP_NAME=$__QL_MUL10X9
techmap -map +/quicklogic/qlf_k6n10f/dspv1_map.v -D USE_DSP_CFG_PARAMS=0
read_verilog -lib +/quicklogic/qlf_k6n10f/dspv1_sim.v
select -assert-count 2 t:dsp_t1_10x9x32_cfg_ports
select -assert-count 0 t:dsp_t1_20x18x64_cfg_ports
equiv_opt -assert -async2sync -map +/quicklogic/qlf_k6n10f/dspv1_sim.v ql_dsp_simd
design -load postopt
select -assert-count 0 t:dsp_t1_10x9x32_cfg_ports
select -assert-count 1 t:dsp_t1_20x18x64_cfg_ports
design -reset
read_verilog <<EOT
module foo(
input [7:0] A,
input [7:0] B,
input [7:0] C,
input [7:0] D,
input [7:0] E,
output reg [7:0] X,
output reg [7:0] Y);
assign X = A * B;
assign Y = C * (D + E); // <-- look here
endmodule
EOT
synth_quicklogic -run :map_dsp
wreduce t:$mul
ql_dsp_macc
techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=20 -D DSP_B_MAXWIDTH=18 -D DSP_A_MINWIDTH=11 -D DSP_B_MINWIDTH=10 -D DSP_NAME=$__QL_MUL20X18
chtype -set $mul t:$__soft_mul
techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=10 -D DSP_B_MAXWIDTH=9 -D DSP_A_MINWIDTH=4 -D DSP_B_MINWIDTH=4 -D DSP_NAME=$__QL_MUL10X9
techmap -map +/quicklogic/qlf_k6n10f/dspv1_map.v -D USE_DSP_CFG_PARAMS=0
read_verilog -lib +/quicklogic/qlf_k6n10f/dspv1_sim.v
select -assert-count 2 t:dsp_t1_10x9x32_cfg_ports
select -assert-count 0 t:dsp_t1_20x18x64_cfg_ports
equiv_opt -assert -async2sync -map +/quicklogic/qlf_k6n10f/dspv1_sim.v ql_dsp_simd
design -load postopt
select -assert-count 0 t:dsp_t1_10x9x32_cfg_ports
select -assert-count 1 t:dsp_t1_20x18x64_cfg_ports