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https://github.com/YosysHQ/yosys
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Add latch mapping.
Co-authored-by: Iztok Jeras <iztok.jeras@gmail.com>
This commit is contained in:
nella
nella
parent
6c6ebb7c08
commit
326d4632fc
4 changed files with 210 additions and 87 deletions
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@ -296,7 +296,10 @@ static bool create_latch(RTLIL::Module *module, const LibertyAst *node, bool fla
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{
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auto [iq_sig, iqn_sig] = find_latch_ff_wires(module, node);
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RTLIL::SigSpec enable_sig, data_sig, clear_sig, preset_sig;
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const std::string name = module->name.unescape();
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std::optional<char> clear_preset_var1;
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std::optional<char> clear_preset_var2;
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for (auto child : node->children) {
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if (child->id == "enable")
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enable_sig = parse_func_expr(module, child->value.c_str());
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@ -306,32 +309,83 @@ static bool create_latch(RTLIL::Module *module, const LibertyAst *node, bool fla
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clear_sig = parse_func_expr(module, child->value.c_str());
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if (child->id == "preset")
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preset_sig = parse_func_expr(module, child->value.c_str());
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for (auto& [id, var] : {pair{"clear_preset_var1", &clear_preset_var1}, {"clear_preset_var2", &clear_preset_var2}}) {
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if (child->id == id) {
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if (child->value.size() != 1)
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log_error("Unexpected length of clear_preset_var* value %s in LATCH cell %s\n", child->value, name);
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*var = child->value[0];
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}
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}
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}
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if (enable_sig.size() == 0 || data_sig.size() == 0) {
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if (!flag_ignore_miss_data_latch)
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log_error("Latch cell %s has no data_in and/or enable attribute.\n", module);
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log_error("LATCH cell %s has no data_in and/or enable attribute.\n", name);
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else
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log("Ignored latch cell %s with no data_in and/or enable attribute.\n", module);
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log("Ignored LATCH cell %s with no data_in and/or enable attribute.\n", name);
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return false;
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}
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RTLIL::Cell *cell = module->addCell(NEW_ID, ID($_NOT_));
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cell->setPort(ID::A, iq_sig);
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cell->setPort(ID::Y, iqn_sig);
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for (auto& [out_sig, cp_var, neg] : {tuple{iq_sig, clear_preset_var1, false}, {iqn_sig, clear_preset_var2, true}}) {
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SigSpec q_sig = out_sig;
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if (neg) {
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q_sig = module->addWire(NEW_ID, out_sig.as_wire());
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module->addNotGate(NEW_ID, q_sig, out_sig);
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}
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if (clear_sig.size() == 1) {
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RTLIL::SigSpec clear_negative = module->NotGate(NEW_ID, clear_sig);
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data_sig = module->AndGate(NEW_ID, data_sig, clear_negative);
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enable_sig = module->OrGate(NEW_ID, enable_sig, clear_sig);
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}
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RTLIL::Cell* cell = module->addCell(NEW_ID, "");
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cell->setPort(ID::D, data_sig);
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cell->setPort(ID::Q, q_sig);
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cell->setPort(ID::E, enable_sig);
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if (preset_sig.size() == 1) {
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data_sig = module->OrGate(NEW_ID, data_sig, preset_sig);
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enable_sig = module->OrGate(NEW_ID, enable_sig, preset_sig);
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if (clear_sig.size() == 0 && preset_sig.size() == 0) {
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cell->type = ID::$_DLATCH_P_;
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}
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if (clear_sig.size() == 1 && preset_sig.size() == 0) {
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cell->type = ID::$_DLATCH_PP0_;
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cell->setPort(ID::R, clear_sig);
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}
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if (clear_sig.size() == 0 && preset_sig.size() == 1) {
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cell->type = ID::$_DLATCH_PP1_;
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cell->setPort(ID::R, preset_sig);
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}
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if (clear_sig.size() == 1 && preset_sig.size() == 1) {
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cell->type = ID::$_DLATCHSR_PPP_;
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SigBit s_sig = preset_sig;
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SigBit r_sig = clear_sig;
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if (cp_var && *cp_var != 'X') {
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// Either set or reset dominates
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bool set_dominates;
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if (*cp_var == 'L') {
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set_dominates = neg;
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} else if (*cp_var == 'H') {
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set_dominates = !neg;
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} else {
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log_error("LATCH cell %s has unsupported clear&preset behavior \'%c\'.\n", name, *cp_var);
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}
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log_debug("cell %s variable %d cp_var %c set dominates? %d\n", name, (int)neg + 1, *cp_var, set_dominates);
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// S&R priority is well-defined now
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if (set_dominates) {
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r_sig = module->AndnotGate(NEW_ID, r_sig, s_sig);
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} else {
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s_sig = module->AndnotGate(NEW_ID, s_sig, r_sig);
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}
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} else {
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log_debug("cell %s variable %d undef c&p behavior\n", name, (int)neg + 1);
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}
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cell->setPort(ID::S, s_sig);
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cell->setPort(ID::R, r_sig);
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}
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log_assert(!cell->type.empty());
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}
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cell = module->addDlatchGate(NEW_ID, enable_sig, data_sig, iq_sig, true);
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return true;
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}
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@ -67,7 +67,7 @@ enum FfInit {
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};
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struct DffLegalizePass : public Pass {
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DffLegalizePass() : Pass("dfflegalize", "convert FFs to types supported by the target") { }
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DffLegalizePass() : Pass("dfflegalize", "convert FFs and LATCHes to types supported by the target") { }
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void help() override
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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@ -1071,7 +1071,7 @@ struct DffLegalizePass : public Pass {
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void execute(std::vector<std::string> args, RTLIL::Design *design) override
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{
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log_header(design, "Executing DFFLEGALIZE pass (convert FFs to types supported by the target).\n");
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log_header(design, "Executing DFFLEGALIZE pass (convert FFs and LATCHes to types supported by the target).\n");
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for (int i = 0; i < NUM_FFTYPES; i++) {
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for (int j = 0; j < NUM_NEG; j++)
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@ -37,7 +37,7 @@ static std::map<RTLIL::IdString, cell_mapping> cell_mappings;
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static void logmap(IdString dff)
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{
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if (cell_mappings.count(dff) == 0) {
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log(" unmapped dff cell: %s\n", dff);
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log(" unmapped dff/dlatch cell: %s\n", dff);
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} else {
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log(" %s %s (", cell_mappings[dff].cell_name, dff.substr(1));
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bool first = true;
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@ -81,6 +81,27 @@ static void logmap_all()
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logmap(ID($_DFFSR_PNP_));
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logmap(ID($_DFFSR_PPN_));
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logmap(ID($_DFFSR_PPP_));
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logmap(ID($_DLATCH_N_));
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logmap(ID($_DLATCH_P_));
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logmap(ID($_DLATCH_NN0_));
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logmap(ID($_DLATCH_NN1_));
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logmap(ID($_DLATCH_NP0_));
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logmap(ID($_DLATCH_NP1_));
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logmap(ID($_DLATCH_PN0_));
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logmap(ID($_DLATCH_PN1_));
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logmap(ID($_DLATCH_PP0_));
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logmap(ID($_DLATCH_PP1_));
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logmap(ID($_DLATCHSR_NNN_));
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logmap(ID($_DLATCHSR_NNP_));
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logmap(ID($_DLATCHSR_NPN_));
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logmap(ID($_DLATCHSR_NPP_));
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logmap(ID($_DLATCHSR_PNN_));
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logmap(ID($_DLATCHSR_PNP_));
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logmap(ID($_DLATCHSR_PPN_));
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logmap(ID($_DLATCHSR_PPP_));
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}
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static bool parse_next_state(const LibertyAst *cell, const LibertyAst *attr, std::string &data_name, bool &data_not_inverted, std::string &enable_name, bool &enable_not_inverted)
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@ -236,10 +257,11 @@ static bool parse_pin(const LibertyAst *cell, const LibertyAst *attr, std::strin
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}
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struct FfSpec {
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bool clkpol = false;
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bool is_latch = false;
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bool ctrlpol = false; // clock for ff, enable for latch
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bool has_reset = false, rstpol = false, rstval = false;
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bool has_sr = false, setpol = false, clrpol = false;
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bool has_enable = false, enapol = false;
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bool has_enable = false, enapol = false; // ff clock enable, not used for latch
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};
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struct BestCell {
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@ -262,7 +284,7 @@ static bool is_dont_use(const LibertyAst *cell, std::vector<std::string> &dont_u
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}
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// scan the cell pins, and if the cell is a better match than the current best, record it
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static void find_better_cell(BestCell &best, const LibertyAst *cell, const LibertyAst *ff, bool cell_next_pol, std::map<std::string, char> &this_cell_ports)
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static void find_better_cell(BestCell &best, const LibertyAst *cell, const LibertyAst *storage, bool data_pol, std::map<std::string, char> &this_cell_ports)
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{
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double area = 0;
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const LibertyAst *ar = cell->find("area");
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@ -290,15 +312,15 @@ static void find_better_cell(BestCell &best, const LibertyAst *cell, const Liber
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std::string value = func->value;
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for (size_t pos = value.find_first_of("\" \t"); pos != std::string::npos; pos = value.find_first_of("\" \t"))
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value.erase(pos, 1);
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if (value == ff->args[0]) {
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this_cell_ports[pin->args[0]] = cell_next_pol ? 'Q' : 'q';
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if (cell_next_pol)
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if (value == storage->args[0]) {
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this_cell_ports[pin->args[0]] = data_pol ? 'Q' : 'q';
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if (data_pol)
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found_noninv_output = true;
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found_output = true;
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} else
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if (value == ff->args[1]) {
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this_cell_ports[pin->args[0]] = cell_next_pol ? 'q' : 'Q';
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if (!cell_next_pol)
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if (value == storage->args[1]) {
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this_cell_ports[pin->args[0]] = data_pol ? 'q' : 'Q';
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if (!data_pol)
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found_noninv_output = true;
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found_output = true;
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}
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@ -327,42 +349,50 @@ static void find_cell(std::vector<const LibertyAst *> cells, IdString cell_type,
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log_assert(!(spec.has_sr && spec.enapol) && "set/reset cell with enable is unimplemented due to lack of cells for testing");
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// ff stores its state in a "ff" group with a "clocked_on" control pin, latch in a "latch" group with an "enable"
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const char *group = spec.is_latch ? "latch" : "ff";
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const char *ctrl_attr = spec.is_latch ? "enable" : "clocked_on";
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for (auto cell : cells)
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{
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if (is_dont_use(cell, dont_use_cells))
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continue;
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const LibertyAst *ff = cell->find("ff");
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if (ff == nullptr)
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const LibertyAst *storage = cell->find(group);
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if (storage == nullptr)
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continue;
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std::string cell_clk_pin, cell_rst_pin, cell_set_pin, cell_clr_pin, cell_next_pin, cell_enable_pin;
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bool cell_clk_pol, cell_rst_pol, cell_set_pol, cell_clr_pol, cell_next_pol, cell_enable_pol;
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std::string cell_ctrl_pin, cell_rst_pin, cell_set_pin, cell_clr_pin, cell_data_pin, cell_enable_pin;
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bool cell_ctrl_pol, cell_rst_pol, cell_set_pol, cell_clr_pol, cell_data_pol, cell_enable_pol;
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if (!parse_pin(cell, ff->find("clocked_on"), cell_clk_pin, cell_clk_pol) || cell_clk_pol != spec.clkpol)
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continue;
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if (!parse_next_state(cell, ff->find("next_state"), cell_next_pin, cell_next_pol, cell_enable_pin, cell_enable_pol) || (spec.has_enable && (cell_enable_pin.empty() || cell_enable_pol != spec.enapol)))
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if (!parse_pin(cell, storage->find(ctrl_attr), cell_ctrl_pin, cell_ctrl_pol) || cell_ctrl_pol != spec.ctrlpol)
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continue;
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if (spec.is_latch) {
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if (!parse_pin(cell, storage->find("data_in"), cell_data_pin, cell_data_pol))
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continue;
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} else {
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if (!parse_next_state(cell, storage->find("next_state"), cell_data_pin, cell_data_pol, cell_enable_pin, cell_enable_pol) || (spec.has_enable && (cell_enable_pin.empty() || cell_enable_pol != spec.enapol)))
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continue;
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}
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std::map<std::string, char> this_cell_ports;
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this_cell_ports[cell_clk_pin] = 'C';
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this_cell_ports[cell_ctrl_pin] = spec.is_latch ? 'E' : 'C';
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if (spec.has_reset) {
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// negated next_state is propagated to the output, which requires negating the reset value
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bool cell_rstval = cell_next_pol ? spec.rstval : !spec.rstval;
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const char *rst_attr = cell_rstval ? "preset" : "clear";
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if (!parse_pin(cell, ff->find(rst_attr), cell_rst_pin, cell_rst_pol) || cell_rst_pol != spec.rstpol)
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// a negated data path is propagated to the output, which requires negating the reset value
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const char *rst_attr = (spec.rstval == cell_data_pol) ? "preset" : "clear";
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if (!parse_pin(cell, storage->find(rst_attr), cell_rst_pin, cell_rst_pol) || cell_rst_pol != spec.rstpol)
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continue;
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this_cell_ports[cell_rst_pin] = 'R';
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}
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if (spec.has_sr) {
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if (!parse_pin(cell, ff->find("preset"), cell_set_pin, cell_set_pol))
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if (!parse_pin(cell, storage->find("preset"), cell_set_pin, cell_set_pol))
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continue;
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if (!parse_pin(cell, ff->find("clear"), cell_clr_pin, cell_clr_pol))
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if (!parse_pin(cell, storage->find("clear"), cell_clr_pin, cell_clr_pol))
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continue;
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if (!cell_next_pol) {
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// negated next_state is propagated to the output, which requires swapping set and reset
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if (!cell_data_pol) {
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// a negated data path is propagated to the output, which requires swapping set and reset
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std::swap(cell_set_pin, cell_clr_pin);
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std::swap(cell_set_pol, cell_clr_pol);
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}
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@ -374,9 +404,9 @@ static void find_cell(std::vector<const LibertyAst *> cells, IdString cell_type,
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if (spec.has_enable)
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this_cell_ports[cell_enable_pin] = 'E';
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this_cell_ports[cell_next_pin] = 'D';
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this_cell_ports[cell_data_pin] = 'D';
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find_better_cell(best, cell, ff, cell_next_pol, this_cell_ports);
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find_better_cell(best, cell, storage, cell_data_pol, this_cell_ports);
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}
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if (best.cell != nullptr) {
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@ -389,7 +419,7 @@ static void find_cell(std::vector<const LibertyAst *> cells, IdString cell_type,
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static void dfflibmap(RTLIL::Design *design, RTLIL::Module *module)
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{
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log("Mapping DFF cells in module `%s':\n", module->name);
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log("Mapping DFF/DLATCH cells in module `%s':\n", module->name);
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dict<SigBit, pool<Cell*>> notmap;
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SigMap sigmap(module);
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@ -467,19 +497,19 @@ static void dfflibmap(RTLIL::Design *design, RTLIL::Module *module)
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}
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struct DfflibmapPass : public Pass {
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DfflibmapPass() : Pass("dfflibmap", "technology mapping of flip-flops") { }
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DfflibmapPass() : Pass("dfflibmap", "technology mapping of flip-flops and latches") { }
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void help() override
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{
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log("\n");
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log(" dfflibmap [-prepare] [-map-only] [-info] [-dont_use <cell_name>] -liberty <file> [selection]\n");
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log("\n");
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log("Map internal flip-flop cells to the flip-flop cells in the technology\n");
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log("library specified in the given liberty files.\n");
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log("Map internal flip-flop and latch cells to the flip-flop and latch cells in the\n");
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log("technology library specified in the given liberty files.\n");
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log("\n");
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log("This pass may add inverters as needed. Therefore it is recommended to\n");
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log("first run this pass and then map the logic paths to the target technology.\n");
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log("\n");
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log("When called with -prepare, this command will convert the internal FF cells\n");
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log("When called with -prepare, this command will convert the internal FF/latch cells\n");
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log("to the internal cell types that best match the cells found in the given\n");
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log("liberty file, but won't actually map them to the target cells.\n");
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log("\n");
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@ -500,7 +530,7 @@ struct DfflibmapPass : public Pass {
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) override
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{
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log_header(design, "Executing DFFLIBMAP pass (mapping DFF cells to sequential cells from liberty file).\n");
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log_header(design, "Executing DFFLIBMAP pass (mapping DFF/DLATCH cells to sequential cells from liberty file).\n");
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log_push();
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bool prepare_mode = false;
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@ -560,39 +590,60 @@ struct DfflibmapPass : public Pass {
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}
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find_cell(merged.cells, ID($_DFF_N_), {}, dont_use_cells);
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find_cell(merged.cells, ID($_DFF_P_), {.clkpol=true}, dont_use_cells);
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find_cell(merged.cells, ID($_DFF_P_), {.ctrlpol=true}, dont_use_cells);
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find_cell(merged.cells, ID($_DFF_NN0_), {.has_reset=true}, dont_use_cells);
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find_cell(merged.cells, ID($_DFF_NN1_), {.has_reset=true, .rstval=true}, dont_use_cells);
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find_cell(merged.cells, ID($_DFF_NP0_), {.has_reset=true, .rstpol=true}, dont_use_cells);
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find_cell(merged.cells, ID($_DFF_NP1_), {.has_reset=true, .rstpol=true, .rstval=true}, dont_use_cells);
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find_cell(merged.cells, ID($_DFF_PN0_), {.clkpol=true, .has_reset=true}, dont_use_cells);
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find_cell(merged.cells, ID($_DFF_PN1_), {.clkpol=true, .has_reset=true, .rstval=true}, dont_use_cells);
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find_cell(merged.cells, ID($_DFF_PP0_), {.clkpol=true, .has_reset=true, .rstpol=true}, dont_use_cells);
|
||||
find_cell(merged.cells, ID($_DFF_PP1_), {.clkpol=true, .has_reset=true, .rstpol=true, .rstval=true}, dont_use_cells);
|
||||
find_cell(merged.cells, ID($_DFF_PN0_), {.ctrlpol=true, .has_reset=true}, dont_use_cells);
|
||||
find_cell(merged.cells, ID($_DFF_PN1_), {.ctrlpol=true, .has_reset=true, .rstval=true}, dont_use_cells);
|
||||
find_cell(merged.cells, ID($_DFF_PP0_), {.ctrlpol=true, .has_reset=true, .rstpol=true}, dont_use_cells);
|
||||
find_cell(merged.cells, ID($_DFF_PP1_), {.ctrlpol=true, .has_reset=true, .rstpol=true, .rstval=true}, dont_use_cells);
|
||||
|
||||
find_cell(merged.cells, ID($_DFFE_NN_), {.has_enable=true}, dont_use_cells);
|
||||
find_cell(merged.cells, ID($_DFFE_NP_), {.has_enable=true, .enapol=true}, dont_use_cells);
|
||||
find_cell(merged.cells, ID($_DFFE_PN_), {.clkpol=true, .has_enable=true}, dont_use_cells);
|
||||
find_cell(merged.cells, ID($_DFFE_PP_), {.clkpol=true, .has_enable=true, .enapol=true}, dont_use_cells);
|
||||
find_cell(merged.cells, ID($_DFFE_PN_), {.ctrlpol=true, .has_enable=true}, dont_use_cells);
|
||||
find_cell(merged.cells, ID($_DFFE_PP_), {.ctrlpol=true, .has_enable=true, .enapol=true}, dont_use_cells);
|
||||
|
||||
find_cell(merged.cells, ID($_DFFSR_NNN_), {.has_sr=true}, dont_use_cells);
|
||||
find_cell(merged.cells, ID($_DFFSR_NNP_), {.has_sr=true, .clrpol=true}, dont_use_cells);
|
||||
find_cell(merged.cells, ID($_DFFSR_NPN_), {.has_sr=true, .setpol=true}, dont_use_cells);
|
||||
find_cell(merged.cells, ID($_DFFSR_NPP_), {.has_sr=true, .setpol=true, .clrpol=true}, dont_use_cells);
|
||||
find_cell(merged.cells, ID($_DFFSR_PNN_), {.clkpol=true, .has_sr=true}, dont_use_cells);
|
||||
find_cell(merged.cells, ID($_DFFSR_PNP_), {.clkpol=true, .has_sr=true, .clrpol=true}, dont_use_cells);
|
||||
find_cell(merged.cells, ID($_DFFSR_PPN_), {.clkpol=true, .has_sr=true, .setpol=true}, dont_use_cells);
|
||||
find_cell(merged.cells, ID($_DFFSR_PPP_), {.clkpol=true, .has_sr=true, .setpol=true, .clrpol=true}, dont_use_cells);
|
||||
find_cell(merged.cells, ID($_DFFSR_PNN_), {.ctrlpol=true, .has_sr=true}, dont_use_cells);
|
||||
find_cell(merged.cells, ID($_DFFSR_PNP_), {.ctrlpol=true, .has_sr=true, .clrpol=true}, dont_use_cells);
|
||||
find_cell(merged.cells, ID($_DFFSR_PPN_), {.ctrlpol=true, .has_sr=true, .setpol=true}, dont_use_cells);
|
||||
find_cell(merged.cells, ID($_DFFSR_PPP_), {.ctrlpol=true, .has_sr=true, .setpol=true, .clrpol=true}, dont_use_cells);
|
||||
|
||||
log(" final dff cell mappings:\n");
|
||||
find_cell(merged.cells, ID($_DLATCH_N_), {.is_latch=true}, dont_use_cells);
|
||||
find_cell(merged.cells, ID($_DLATCH_P_), {.is_latch=true, .ctrlpol=true}, dont_use_cells);
|
||||
|
||||
find_cell(merged.cells, ID($_DLATCH_NN0_), {.is_latch=true, .has_reset=true}, dont_use_cells);
|
||||
find_cell(merged.cells, ID($_DLATCH_NN1_), {.is_latch=true, .has_reset=true, .rstval=true}, dont_use_cells);
|
||||
find_cell(merged.cells, ID($_DLATCH_NP0_), {.is_latch=true, .has_reset=true, .rstpol=true}, dont_use_cells);
|
||||
find_cell(merged.cells, ID($_DLATCH_NP1_), {.is_latch=true, .has_reset=true, .rstpol=true, .rstval=true}, dont_use_cells);
|
||||
find_cell(merged.cells, ID($_DLATCH_PN0_), {.is_latch=true, .ctrlpol=true, .has_reset=true}, dont_use_cells);
|
||||
find_cell(merged.cells, ID($_DLATCH_PN1_), {.is_latch=true, .ctrlpol=true, .has_reset=true, .rstval=true}, dont_use_cells);
|
||||
find_cell(merged.cells, ID($_DLATCH_PP0_), {.is_latch=true, .ctrlpol=true, .has_reset=true, .rstpol=true}, dont_use_cells);
|
||||
find_cell(merged.cells, ID($_DLATCH_PP1_), {.is_latch=true, .ctrlpol=true, .has_reset=true, .rstpol=true, .rstval=true}, dont_use_cells);
|
||||
|
||||
find_cell(merged.cells, ID($_DLATCHSR_NNN_), {.is_latch=true, .has_sr=true}, dont_use_cells);
|
||||
find_cell(merged.cells, ID($_DLATCHSR_NNP_), {.is_latch=true, .has_sr=true, .clrpol=true}, dont_use_cells);
|
||||
find_cell(merged.cells, ID($_DLATCHSR_NPN_), {.is_latch=true, .has_sr=true, .setpol=true}, dont_use_cells);
|
||||
find_cell(merged.cells, ID($_DLATCHSR_NPP_), {.is_latch=true, .has_sr=true, .setpol=true, .clrpol=true}, dont_use_cells);
|
||||
find_cell(merged.cells, ID($_DLATCHSR_PNN_), {.is_latch=true, .ctrlpol=true, .has_sr=true}, dont_use_cells);
|
||||
find_cell(merged.cells, ID($_DLATCHSR_PNP_), {.is_latch=true, .ctrlpol=true, .has_sr=true, .clrpol=true}, dont_use_cells);
|
||||
find_cell(merged.cells, ID($_DLATCHSR_PPN_), {.is_latch=true, .ctrlpol=true, .has_sr=true, .setpol=true}, dont_use_cells);
|
||||
find_cell(merged.cells, ID($_DLATCHSR_PPP_), {.is_latch=true, .ctrlpol=true, .has_sr=true, .setpol=true, .clrpol=true}, dont_use_cells);
|
||||
|
||||
log(" final dff/dlatch cell mappings:\n");
|
||||
logmap_all();
|
||||
|
||||
if (!map_only_mode) {
|
||||
std::string dfflegalize_cmd = "dfflegalize";
|
||||
for (auto it : cell_mappings)
|
||||
dfflegalize_cmd += stringf(" -cell %s 01", it.first);
|
||||
dfflegalize_cmd += " t:$_DFF* t:$_SDFF*";
|
||||
dfflegalize_cmd += " t:$_DFF* t:$_SDFF* t:$_DLATCH*";
|
||||
if (info_mode) {
|
||||
log("dfflegalize command line: %s\n", dfflegalize_cmd);
|
||||
} else {
|
||||
|
|
|
|||
|
|
@ -1,29 +1,47 @@
|
|||
|
||||
-- Running command `dfflibmap -info -liberty dff.lib' --
|
||||
|
||||
1. Executing DFFLIBMAP pass (mapping DFF cells to sequential cells from liberty file).
|
||||
1. Executing DFFLIBMAP pass (mapping DFF/DLATCH cells to sequential cells from liberty file).
|
||||
cell dff (noninv, pins=3, area=1.00) is a direct match for cell type $_DFF_P_.
|
||||
final dff cell mappings:
|
||||
unmapped dff cell: $_DFF_N_
|
||||
final dff/dlatch cell mappings:
|
||||
unmapped dff/dlatch cell: $_DFF_N_
|
||||
\dff _DFF_P_ (.CLK( C), .D( D), .Q( Q));
|
||||
unmapped dff cell: $_DFF_NN0_
|
||||
unmapped dff cell: $_DFF_NN1_
|
||||
unmapped dff cell: $_DFF_NP0_
|
||||
unmapped dff cell: $_DFF_NP1_
|
||||
unmapped dff cell: $_DFF_PN0_
|
||||
unmapped dff cell: $_DFF_PN1_
|
||||
unmapped dff cell: $_DFF_PP0_
|
||||
unmapped dff cell: $_DFF_PP1_
|
||||
unmapped dff cell: $_DFFE_NN_
|
||||
unmapped dff cell: $_DFFE_NP_
|
||||
unmapped dff cell: $_DFFE_PN_
|
||||
unmapped dff cell: $_DFFE_PP_
|
||||
unmapped dff cell: $_DFFSR_NNN_
|
||||
unmapped dff cell: $_DFFSR_NNP_
|
||||
unmapped dff cell: $_DFFSR_NPN_
|
||||
unmapped dff cell: $_DFFSR_NPP_
|
||||
unmapped dff cell: $_DFFSR_PNN_
|
||||
unmapped dff cell: $_DFFSR_PNP_
|
||||
unmapped dff cell: $_DFFSR_PPN_
|
||||
unmapped dff cell: $_DFFSR_PPP_
|
||||
dfflegalize command line: dfflegalize -cell $_DFF_P_ 01 t:$_DFF* t:$_SDFF*
|
||||
unmapped dff/dlatch cell: $_DFF_NN0_
|
||||
unmapped dff/dlatch cell: $_DFF_NN1_
|
||||
unmapped dff/dlatch cell: $_DFF_NP0_
|
||||
unmapped dff/dlatch cell: $_DFF_NP1_
|
||||
unmapped dff/dlatch cell: $_DFF_PN0_
|
||||
unmapped dff/dlatch cell: $_DFF_PN1_
|
||||
unmapped dff/dlatch cell: $_DFF_PP0_
|
||||
unmapped dff/dlatch cell: $_DFF_PP1_
|
||||
unmapped dff/dlatch cell: $_DFFE_NN_
|
||||
unmapped dff/dlatch cell: $_DFFE_NP_
|
||||
unmapped dff/dlatch cell: $_DFFE_PN_
|
||||
unmapped dff/dlatch cell: $_DFFE_PP_
|
||||
unmapped dff/dlatch cell: $_DFFSR_NNN_
|
||||
unmapped dff/dlatch cell: $_DFFSR_NNP_
|
||||
unmapped dff/dlatch cell: $_DFFSR_NPN_
|
||||
unmapped dff/dlatch cell: $_DFFSR_NPP_
|
||||
unmapped dff/dlatch cell: $_DFFSR_PNN_
|
||||
unmapped dff/dlatch cell: $_DFFSR_PNP_
|
||||
unmapped dff/dlatch cell: $_DFFSR_PPN_
|
||||
unmapped dff/dlatch cell: $_DFFSR_PPP_
|
||||
unmapped dff/dlatch cell: $_DLATCH_N_
|
||||
unmapped dff/dlatch cell: $_DLATCH_P_
|
||||
unmapped dff/dlatch cell: $_DLATCH_NN0_
|
||||
unmapped dff/dlatch cell: $_DLATCH_NN1_
|
||||
unmapped dff/dlatch cell: $_DLATCH_NP0_
|
||||
unmapped dff/dlatch cell: $_DLATCH_NP1_
|
||||
unmapped dff/dlatch cell: $_DLATCH_PN0_
|
||||
unmapped dff/dlatch cell: $_DLATCH_PN1_
|
||||
unmapped dff/dlatch cell: $_DLATCH_PP0_
|
||||
unmapped dff/dlatch cell: $_DLATCH_PP1_
|
||||
unmapped dff/dlatch cell: $_DLATCHSR_NNN_
|
||||
unmapped dff/dlatch cell: $_DLATCHSR_NNP_
|
||||
unmapped dff/dlatch cell: $_DLATCHSR_NPN_
|
||||
unmapped dff/dlatch cell: $_DLATCHSR_NPP_
|
||||
unmapped dff/dlatch cell: $_DLATCHSR_PNN_
|
||||
unmapped dff/dlatch cell: $_DLATCHSR_PNP_
|
||||
unmapped dff/dlatch cell: $_DLATCHSR_PPN_
|
||||
unmapped dff/dlatch cell: $_DLATCHSR_PPP_
|
||||
dfflegalize command line: dfflegalize -cell $_DFF_P_ 01 t:$_DFF* t:$_SDFF* t:$_DLATCH*
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue