diff --git a/tests/arch/ice40/memories.ys b/tests/arch/ice40/memories.ys
deleted file mode 100644
index d480a3abe..000000000
--- a/tests/arch/ice40/memories.ys
+++ /dev/null
@@ -1,138 +0,0 @@
-# ================================ RAM ================================
-# RAM bits <= 4K; Data width <= 16; Address width <= 11: -> SB_RAM40_4K
-
-design -reset; read_verilog -defer ../common/blockram.v
-chparam -set ADDRESS_WIDTH 11 -set DATA_WIDTH 2 sync_ram_sdp
-hierarchy -top sync_ram_sdp
-synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp
-select -assert-count 1 t:SB_RAM40_4K
-
-design -reset; read_verilog -defer ../common/blockram.v
-chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 4 sync_ram_sdp
-hierarchy -top sync_ram_sdp
-synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp
-select -assert-count 1 t:SB_RAM40_4K
-
-design -reset; read_verilog -defer ../common/blockram.v
-chparam -set ADDRESS_WIDTH 9 -set DATA_WIDTH 8 sync_ram_sdp
-hierarchy -top sync_ram_sdp
-synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp
-select -assert-count 1 t:SB_RAM40_4K
-
-design -reset; read_verilog -defer ../common/blockram.v
-chparam -set ADDRESS_WIDTH 8 -set DATA_WIDTH 16 sync_ram_sdp
-hierarchy -top sync_ram_sdp
-synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp
-select -assert-count 1 t:SB_RAM40_4K
-
-## With parameters
-
-design -reset; read_verilog -defer ../common/blockram.v
-chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_ram_sdp
-hierarchy -top sync_ram_sdp
-synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp
-select -assert-count 0 t:SB_RAM40_4K # too inefficient
-select -assert-min 1 t:SB_DFFE
-
-design -reset; read_verilog -defer ../common/blockram.v
-chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_ram_sdp
-hierarchy -top sync_ram_sdp
-setattr -set syn_ramstyle "block_ram" m:memory
-synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp
-select -assert-count 1 t:SB_RAM40_4K
-
-design -reset; read_verilog -defer ../common/blockram.v
-chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_ram_sdp
-hierarchy -top sync_ram_sdp
-setattr -set syn_ramstyle "Block_RAM" m:memory
-synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp
-select -assert-count 1 t:SB_RAM40_4K # any case works
-
-design -reset; read_verilog -defer ../common/blockram.v
-chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_ram_sdp
-hierarchy -top sync_ram_sdp
-setattr -set ram_block 1 m:memory
-synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp
-select -assert-count 1 t:SB_RAM40_4K
-
-design -reset; read_verilog -defer ../common/blockram.v
-chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_ram_sdp
-hierarchy -top sync_ram_sdp
-setattr -set syn_ramstyle "registers" m:memory
-synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp
-select -assert-count 0 t:SB_RAM40_4K # requested FFRAM explicitly
-select -assert-min 1 t:SB_DFFE
-
-design -reset; read_verilog -defer ../common/blockram.v
-chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_ram_sdp
-hierarchy -top sync_ram_sdp
-setattr -set logic_block 1 m:memory
-synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp
-select -assert-count 0 t:SB_RAM40_4K # requested FFRAM explicitly
-select -assert-min 1 t:SB_DFFE
-
-# ================================ ROM ================================
-# ROM bits <= 4K; Data width <= 16; Address width <= 11: -> SB_RAM40_4K
-
-design -reset; read_verilog -defer ../common/blockrom.v
-chparam -set ADDRESS_WIDTH 11 -set DATA_WIDTH 2 sync_rom
-hierarchy -top sync_rom
-synth_ice40 -top sync_rom; cd sync_rom
-select -assert-count 1 t:SB_RAM40_4K
-
-design -reset; read_verilog -defer ../common/blockrom.v
-chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 4 sync_rom
-hierarchy -top sync_rom
-synth_ice40 -top sync_rom; cd sync_rom
-select -assert-count 1 t:SB_RAM40_4K
-
-design -reset; read_verilog -defer ../common/blockrom.v
-chparam -set ADDRESS_WIDTH 9 -set DATA_WIDTH 8 sync_rom
-hierarchy -top sync_rom
-synth_ice40 -top sync_rom; cd sync_rom
-select -assert-count 1 t:SB_RAM40_4K
-
-design -reset; read_verilog -defer ../common/blockrom.v
-chparam -set ADDRESS_WIDTH 8 -set DATA_WIDTH 16 sync_rom
-hierarchy -top sync_rom
-synth_ice40 -top sync_rom; cd sync_rom
-select -assert-count 1 t:SB_RAM40_4K
-
-## With parameters
-
-design -reset; read_verilog -defer ../common/blockrom.v
-chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_rom
-hierarchy -top sync_rom
-synth_ice40 -top sync_rom; cd sync_rom
-select -assert-count 0 t:SB_RAM40_4K # too inefficient
-select -assert-min 1 t:SB_LUT4
-
-design -reset; read_verilog -defer ../common/blockrom.v
-chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_rom
-hierarchy -top sync_rom
-setattr -set syn_romstyle "ebr" m:memory
-synth_ice40 -top sync_rom; cd sync_rom
-select -assert-count 1 t:SB_RAM40_4K
-
-design -reset; read_verilog -defer ../common/blockrom.v
-chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_rom
-hierarchy -top sync_rom
-setattr -set rom_block 1 m:memory
-synth_ice40 -top sync_rom; cd sync_rom
-select -assert-count 1 t:SB_RAM40_4K
-
-design -reset; read_verilog -defer ../common/blockrom.v
-chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_rom
-hierarchy -top sync_rom
-setattr -set syn_romstyle "logic" m:memory
-synth_ice40 -top sync_rom; cd sync_rom
-select -assert-count 0 t:SB_RAM40_4K # requested LUTROM explicitly
-select -assert-min 1 t:SB_LUT4
-
-design -reset; read_verilog -defer ../common/blockrom.v
-chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_rom
-hierarchy -top sync_rom
-setattr -set logic_block 1 m:memory
-synth_ice40 -top sync_rom; cd sync_rom
-select -assert-count 0 t:SB_RAM40_4K # requested LUTROM explicitly
-select -assert-min 1 t:SB_LUT4
diff --git a/tests/arch/ice40/memories_ram.ys b/tests/arch/ice40/memories_ram.ys
new file mode 100644
index 000000000..29537f8d2
--- /dev/null
+++ b/tests/arch/ice40/memories_ram.ys
@@ -0,0 +1,26 @@
+# ================================ RAM ================================
+# RAM bits <= 4K; Data width <= 16; Address width <= 11: -> SB_RAM40_4K
+
+design -reset; read_verilog -defer ../common/blockram.v
+chparam -set ADDRESS_WIDTH 11 -set DATA_WIDTH 2 sync_ram_sdp
+hierarchy -top sync_ram_sdp
+synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp
+select -assert-count 1 t:SB_RAM40_4K
+
+design -reset; read_verilog -defer ../common/blockram.v
+chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 4 sync_ram_sdp
+hierarchy -top sync_ram_sdp
+synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp
+select -assert-count 1 t:SB_RAM40_4K
+
+design -reset; read_verilog -defer ../common/blockram.v
+chparam -set ADDRESS_WIDTH 9 -set DATA_WIDTH 8 sync_ram_sdp
+hierarchy -top sync_ram_sdp
+synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp
+select -assert-count 1 t:SB_RAM40_4K
+
+design -reset; read_verilog -defer ../common/blockram.v
+chparam -set ADDRESS_WIDTH 8 -set DATA_WIDTH 16 sync_ram_sdp
+hierarchy -top sync_ram_sdp
+synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp
+select -assert-count 1 t:SB_RAM40_4K
diff --git a/tests/arch/ice40/memories_ram_p.ys b/tests/arch/ice40/memories_ram_p.ys
new file mode 100644
index 000000000..1cfdd62b4
--- /dev/null
+++ b/tests/arch/ice40/memories_ram_p.ys
@@ -0,0 +1,48 @@
+# ================================ RAM ================================
+# RAM bits <= 4K; Data width <= 16; Address width <= 11: -> SB_RAM40_4K
+
+## With parameters
+
+design -reset; read_verilog -defer ../common/blockram.v
+chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_ram_sdp
+hierarchy -top sync_ram_sdp
+synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp
+select -assert-count 0 t:SB_RAM40_4K # too inefficient
+select -assert-min 1 t:SB_DFFE
+
+design -reset; read_verilog -defer ../common/blockram.v
+chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_ram_sdp
+hierarchy -top sync_ram_sdp
+setattr -set syn_ramstyle "block_ram" m:memory
+synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp
+select -assert-count 1 t:SB_RAM40_4K
+
+design -reset; read_verilog -defer ../common/blockram.v
+chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_ram_sdp
+hierarchy -top sync_ram_sdp
+setattr -set syn_ramstyle "Block_RAM" m:memory
+synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp
+select -assert-count 1 t:SB_RAM40_4K # any case works
+
+design -reset; read_verilog -defer ../common/blockram.v
+chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_ram_sdp
+hierarchy -top sync_ram_sdp
+setattr -set ram_block 1 m:memory
+synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp
+select -assert-count 1 t:SB_RAM40_4K
+
+design -reset; read_verilog -defer ../common/blockram.v
+chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_ram_sdp
+hierarchy -top sync_ram_sdp
+setattr -set syn_ramstyle "registers" m:memory
+synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp
+select -assert-count 0 t:SB_RAM40_4K # requested FFRAM explicitly
+select -assert-min 1 t:SB_DFFE
+
+design -reset; read_verilog -defer ../common/blockram.v
+chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_ram_sdp
+hierarchy -top sync_ram_sdp
+setattr -set logic_block 1 m:memory
+synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp
+select -assert-count 0 t:SB_RAM40_4K # requested FFRAM explicitly
+select -assert-min 1 t:SB_DFFE
diff --git a/tests/arch/ice40/memories_rom.ys b/tests/arch/ice40/memories_rom.ys
new file mode 100644
index 000000000..07e96c2fc
--- /dev/null
+++ b/tests/arch/ice40/memories_rom.ys
@@ -0,0 +1,26 @@
+# ================================ ROM ================================
+# ROM bits <= 4K; Data width <= 16; Address width <= 11: -> SB_RAM40_4K
+
+design -reset; read_verilog -defer ../common/blockrom.v
+chparam -set ADDRESS_WIDTH 11 -set DATA_WIDTH 2 sync_rom
+hierarchy -top sync_rom
+synth_ice40 -top sync_rom; cd sync_rom
+select -assert-count 1 t:SB_RAM40_4K
+
+design -reset; read_verilog -defer ../common/blockrom.v
+chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 4 sync_rom
+hierarchy -top sync_rom
+synth_ice40 -top sync_rom; cd sync_rom
+select -assert-count 1 t:SB_RAM40_4K
+
+design -reset; read_verilog -defer ../common/blockrom.v
+chparam -set ADDRESS_WIDTH 9 -set DATA_WIDTH 8 sync_rom
+hierarchy -top sync_rom
+synth_ice40 -top sync_rom; cd sync_rom
+select -assert-count 1 t:SB_RAM40_4K
+
+design -reset; read_verilog -defer ../common/blockrom.v
+chparam -set ADDRESS_WIDTH 8 -set DATA_WIDTH 16 sync_rom
+hierarchy -top sync_rom
+synth_ice40 -top sync_rom; cd sync_rom
+select -assert-count 1 t:SB_RAM40_4K
diff --git a/tests/arch/ice40/memories_rom_p.ys b/tests/arch/ice40/memories_rom_p.ys
new file mode 100644
index 000000000..1bb0dcd19
--- /dev/null
+++ b/tests/arch/ice40/memories_rom_p.ys
@@ -0,0 +1,41 @@
+# ================================ ROM ================================
+# ROM bits <= 4K; Data width <= 16; Address width <= 11: -> SB_RAM40_4K
+
+## With parameters
+
+design -reset; read_verilog -defer ../common/blockrom.v
+chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_rom
+hierarchy -top sync_rom
+synth_ice40 -top sync_rom; cd sync_rom
+select -assert-count 0 t:SB_RAM40_4K # too inefficient
+select -assert-min 1 t:SB_LUT4
+
+design -reset; read_verilog -defer ../common/blockrom.v
+chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_rom
+hierarchy -top sync_rom
+setattr -set syn_romstyle "ebr" m:memory
+synth_ice40 -top sync_rom; cd sync_rom
+select -assert-count 1 t:SB_RAM40_4K
+
+design -reset; read_verilog -defer ../common/blockrom.v
+chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_rom
+hierarchy -top sync_rom
+setattr -set rom_block 1 m:memory
+synth_ice40 -top sync_rom; cd sync_rom
+select -assert-count 1 t:SB_RAM40_4K
+
+design -reset; read_verilog -defer ../common/blockrom.v
+chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_rom
+hierarchy -top sync_rom
+setattr -set syn_romstyle "logic" m:memory
+synth_ice40 -top sync_rom; cd sync_rom
+select -assert-count 0 t:SB_RAM40_4K # requested LUTROM explicitly
+select -assert-min 1 t:SB_LUT4
+
+design -reset; read_verilog -defer ../common/blockrom.v
+chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_rom
+hierarchy -top sync_rom
+setattr -set logic_block 1 m:memory
+synth_ice40 -top sync_rom; cd sync_rom
+select -assert-count 0 t:SB_RAM40_4K # requested LUTROM explicitly
+select -assert-min 1 t:SB_LUT4