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use the new isPublic() in a few places

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This commit is contained in:
N. Engelhardt 2020-09-14 12:43:18 +02:00
parent 4af04be0b7
commit 3238190797
13 changed files with 25 additions and 25 deletions
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4
passes/cmds/rename.cc
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@ -290,11 +290,11 @@ struct RenamePass : public Pass {
dict<RTLIL::Cell *, IdString> new_cell_names;
for (auto wire : module->selected_wires())
if (wire->name[0] == '\\' && wire->port_id == 0)
if (wire->name.isPublic() && wire->port_id == 0)
new_wire_names[wire] = NEW_ID;
for (auto cell : module->selected_cells())
if (cell->name[0] == '\\')
if (cell->name.isPublic())
new_cell_names[cell] = NEW_ID;
for (auto &it : new_wire_names)

2
passes/cmds/show.cc
View file

@ -368,7 +368,7 @@ struct ShowWorker
const char *shape = "diamond";
if (wire->port_input || wire->port_output)
shape = "octagon";
if (wire->name[0] == '\\') {
if (wire->name.isPublic()) {
fprintf(f, "n%d [ shape=%s, label=\"%s\", %s, fontcolor=\"black\" ];\n",
id2num(wire->name), shape, findLabel(wire->name.str()),
nextColor(RTLIL::SigSpec(wire), "color=\"black\"").c_str());

2
passes/cmds/splice.cc
View file

@ -211,7 +211,7 @@ struct SpliceWorker
std::vector<Wire*> mod_wires = module->wires();
for (auto wire : mod_wires)
if ((!no_outputs && wire->port_output) || (do_wires && wire->name[0] == '\\')) {
if ((!no_outputs && wire->port_output) || (do_wires && wire->name.isPublic())) {
if (!design->selected(module, wire))
continue;
RTLIL::SigSpec sig = sigmap(wire);

2
passes/cmds/stat.cc
View file

@ -81,7 +81,7 @@ struct statdata_t
for (auto wire : mod->selected_wires())
{
if (wire->name[0] == '\\') {
if (wire->name.isPublic()) {
num_pub_wires++;
num_pub_wire_bits += wire->width;
}