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https://github.com/YosysHQ/yosys
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use the new isPublic() in a few places
This commit is contained in:
parent
4af04be0b7
commit
3238190797
13 changed files with 25 additions and 25 deletions
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@ -290,11 +290,11 @@ struct RenamePass : public Pass {
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dict<RTLIL::Cell *, IdString> new_cell_names;
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for (auto wire : module->selected_wires())
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if (wire->name[0] == '\\' && wire->port_id == 0)
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if (wire->name.isPublic() && wire->port_id == 0)
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new_wire_names[wire] = NEW_ID;
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for (auto cell : module->selected_cells())
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if (cell->name[0] == '\\')
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if (cell->name.isPublic())
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new_cell_names[cell] = NEW_ID;
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for (auto &it : new_wire_names)
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@ -368,7 +368,7 @@ struct ShowWorker
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const char *shape = "diamond";
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if (wire->port_input || wire->port_output)
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shape = "octagon";
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if (wire->name[0] == '\\') {
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if (wire->name.isPublic()) {
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fprintf(f, "n%d [ shape=%s, label=\"%s\", %s, fontcolor=\"black\" ];\n",
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id2num(wire->name), shape, findLabel(wire->name.str()),
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nextColor(RTLIL::SigSpec(wire), "color=\"black\"").c_str());
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@ -211,7 +211,7 @@ struct SpliceWorker
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std::vector<Wire*> mod_wires = module->wires();
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for (auto wire : mod_wires)
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if ((!no_outputs && wire->port_output) || (do_wires && wire->name[0] == '\\')) {
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if ((!no_outputs && wire->port_output) || (do_wires && wire->name.isPublic())) {
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if (!design->selected(module, wire))
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continue;
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RTLIL::SigSpec sig = sigmap(wire);
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@ -81,7 +81,7 @@ struct statdata_t
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for (auto wire : mod->selected_wires())
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{
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if (wire->name[0] == '\\') {
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if (wire->name.isPublic()) {
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num_pub_wires++;
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num_pub_wire_bits += wire->width;
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}
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@ -114,25 +114,25 @@ struct EquivMakeWorker
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Module *gate_clone = gate_mod->clone();
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for (auto it : gold_clone->wires().to_vector()) {
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if ((it->name[0] == '\\' || inames) && blacklist_names.count(it->name) == 0)
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if ((it->name.isPublic() || inames) && blacklist_names.count(it->name) == 0)
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wire_names.insert(it->name);
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gold_clone->rename(it, it->name.str() + "_gold");
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}
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for (auto it : gold_clone->cells().to_vector()) {
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if ((it->name[0] == '\\' || inames) && blacklist_names.count(it->name) == 0)
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if ((it->name.isPublic() || inames) && blacklist_names.count(it->name) == 0)
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cell_names.insert(it->name);
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gold_clone->rename(it, it->name.str() + "_gold");
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}
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for (auto it : gate_clone->wires().to_vector()) {
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if ((it->name[0] == '\\' || inames) && blacklist_names.count(it->name) == 0)
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if ((it->name.isPublic() || inames) && blacklist_names.count(it->name) == 0)
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wire_names.insert(it->name);
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gate_clone->rename(it, it->name.str() + "_gate");
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}
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for (auto it : gate_clone->cells().to_vector()) {
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if ((it->name[0] == '\\' || inames) && blacklist_names.count(it->name) == 0)
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if ((it->name.isPublic() || inames) && blacklist_names.count(it->name) == 0)
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cell_names.insert(it->name);
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gate_clone->rename(it, it->name.str() + "_gate");
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}
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@ -35,7 +35,7 @@ struct EquivPurgeWorker
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{
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if (sig.is_wire()) {
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Wire *wire = sig.as_wire();
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if (wire->name[0] == '\\') {
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if (wire->name.isPublic()) {
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if (!wire->port_output) {
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log(" Module output: %s (%s)\n", log_signal(wire), log_id(cellname));
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wire->port_output = true;
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@ -62,7 +62,7 @@ struct EquivPurgeWorker
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{
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if (sig.is_wire()) {
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Wire *wire = sig.as_wire();
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if (wire->name[0] == '\\') {
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if (wire->name.isPublic()) {
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if (!wire->port_output) {
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log(" Module input: %s\n", log_signal(wire));
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wire->port_input = true;
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@ -207,7 +207,7 @@ bool compare_signals(RTLIL::SigBit &s1, RTLIL::SigBit &s2, SigPool ®s, SigPoo
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if ((w1->port_input && w1->port_output) != (w2->port_input && w2->port_output))
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return !(w2->port_input && w2->port_output);
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if (w1->name[0] == '\\' && w2->name[0] == '\\') {
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if (w1->name.isPublic() && w2->name.isPublic()) {
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if (regs.check(s1) != regs.check(s2))
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return regs.check(s2);
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if (direct_wires.count(w1) != direct_wires.count(w2))
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@ -220,7 +220,7 @@ bool compare_signals(RTLIL::SigBit &s1, RTLIL::SigBit &s2, SigPool ®s, SigPoo
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return w2->port_output;
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if (w1->name[0] != w2->name[0])
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return w2->name[0] == '\\';
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return w2->name.isPublic();
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int attrs1 = count_nontrivial_wire_attrs(w1);
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int attrs2 = count_nontrivial_wire_attrs(w2);
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@ -439,7 +439,7 @@ void mutate_list(Design *design, const mutate_opts_t &opts, const string &filena
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dict<SigBit, int> bit_user_cnt;
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for (auto wire : module->wires()) {
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if (wire->name[0] == '\\' && wire->attributes.count(ID::src))
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if (wire->name.isPublic() && wire->attributes.count(ID::src))
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sigmap.add(wire);
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}
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@ -468,7 +468,7 @@ void mutate_list(Design *design, const mutate_opts_t &opts, const string &filena
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}
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if (!bit.wire->name[0] != !sigbit.wire->name[0]) {
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if (bit.wire->name[0] == '\\')
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if (bit.wire->name.isPublic())
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sigmap.add(bit);
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continue;
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}
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@ -493,7 +493,7 @@ void mutate_list(Design *design, const mutate_opts_t &opts, const string &filena
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entry.src.insert(s);
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SigBit bit = sigmap(conn.second[i]);
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if (bit.wire && bit.wire->name[0] == '\\' && (cell->output(conn.first) || bit_user_cnt[bit] == 1)) {
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if (bit.wire && bit.wire->name.isPublic() && (cell->output(conn.first) || bit_user_cnt[bit] == 1)) {
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for (auto &s : bit.wire->get_strpool_attribute(ID::src))
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entry.src.insert(s);
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entry.wire = bit.wire->name;
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@ -1365,7 +1365,7 @@ struct SatPass : public Pass {
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if (show_public) {
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for (auto wire : module->wires())
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if (wire->name[0] == '\\')
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if (wire->name.isPublic())
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shows.push_back(wire->name.str());
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}
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