mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-05 17:14:08 +00:00
Code Activity

Merge pull request #4065 from daglem/fix-AST_SHIFT-AST_SHIFTX

Browse source 
Respect the sign of the right operand of AST_SHIFT and AST_SHIFTX
This commit is contained in:
Martin Povišer 2023-12-12 11:47:29 +01:00 committed by GitHub
parent 7bded221a7 cda470d63e
commit 320e75a3e3
No known key found for this signature in database
GPG key ID: 4AEE18F83AFDEB23
1 changed files with 2 additions and 1 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

3
frontends/ast/genrtlil.cc
View file

@ -1740,7 +1740,8 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
if (width_hint < 0)
detectSignWidth(width_hint, sign_hint);
RTLIL::SigSpec left = children[0]->genRTLIL(width_hint, sign_hint);
RTLIL::SigSpec right = children[1]->genRTLIL();
// for $shift and $shiftx, the second operand can be negative
RTLIL::SigSpec right = children[1]->genRTLIL(-1, type == AST_SHIFT || type == AST_SHIFTX);
int width = width_hint > 0 ? width_hint : left.size();
is_signed = children[0]->is_signed;
return binop2rtlil(this, type_name, width, left, right);