From 31f943513bbee5905fc1241fe9edf1dbe24f3110 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Mon, 25 Mar 2024 09:23:31 +0100
Subject: [PATCH] set add_carry property and all inputs to 0
---
techlibs/nanoxplore/nx_carry.cc | 37 ++++++++++++++++++++++++++++++++-
1 file changed, 36 insertions(+), 1 deletion(-)
diff --git a/techlibs/nanoxplore/nx_carry.cc b/techlibs/nanoxplore/nx_carry.cc
index 2a495e41e..a61921e05 100644
--- a/techlibs/nanoxplore/nx_carry.cc
+++ b/techlibs/nanoxplore/nx_carry.cc
@@ -83,6 +83,16 @@ static void nx_carry_chain(Module *module)
if (c.second.at(0)->getPort(ID(CI)).is_wire()) {
cell = module->addCell(NEW_ID, ID(NX_CY));
cell->setPort(ID(CI), State::S0);
+ // Set all inputs on 0
+ cell->setPort(ID(A1), State::S0);
+ cell->setPort(ID(B1), State::S0);
+ cell->setPort(ID(A2), State::S0);
+ cell->setPort(ID(B2), State::S0);
+ cell->setPort(ID(A3), State::S0);
+ cell->setPort(ID(B3), State::S0);
+ cell->setPort(ID(A4), State::S0);
+ cell->setPort(ID(B4), State::S0);
+
cell->setPort(names_A[0], c.second.at(0)->getPort(ID(CI)).as_bit());
cell->setPort(names_B[0], State::S0);
j++;
@@ -91,7 +101,25 @@ static void nx_carry_chain(Module *module)
for (size_t i=0 ; i<c.second.size(); i++) {
if (j==0) {
cell = module->addCell(NEW_ID, ID(NX_CY));
- cell->setPort(ID(CI), c.second.at(i)->getPort(ID(CI)));
+ SigBit ci = c.second.at(i)->getPort(ID(CI)).as_bit();
+ cell->setPort(ID(CI), ci);
+ // Set all inputs on 0
+ cell->setPort(ID(A1), State::S0);
+ cell->setPort(ID(B1), State::S0);
+ cell->setPort(ID(A2), State::S0);
+ cell->setPort(ID(B2), State::S0);
+ cell->setPort(ID(A3), State::S0);
+ cell->setPort(ID(B3), State::S0);
+ cell->setPort(ID(A4), State::S0);
+ cell->setPort(ID(B4), State::S0);
+ if (ci.is_wire()) {
+ cell->setParam(ID(add_carry), Const(2,2));
+ } else {
+ if (ci == State::S0)
+ cell->setParam(ID(add_carry), Const(0,2));
+ else
+ cell->setParam(ID(add_carry), Const(1,2));
+ }
}
if (j==3) {
cell->set_string_attribute(ID(cnt), std::to_string(cnt));
@@ -104,6 +132,13 @@ static void nx_carry_chain(Module *module)
cell->setPort(ID(CI), State::S0);
cell->setPort(ID(A1), new_co);
cell->setPort(ID(B1), State::S0);
+ // Set all inputs on 0
+ cell->setPort(ID(A2), State::S0);
+ cell->setPort(ID(B2), State::S0);
+ cell->setPort(ID(A3), State::S0);
+ cell->setPort(ID(B3), State::S0);
+ cell->setPort(ID(A4), State::S0);
+ cell->setPort(ID(B4), State::S0);
j = 1;
} else {
if (c.second.at(i)->hasPort(ID(CO)))