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Fix handling of unclocked immediate assertions in Verific front-end

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Signed-off-by: Clifford Wolf <clifford@clifford.at>
This commit is contained in:
Clifford Wolf 2018-03-26 13:04:10 +02:00
parent 3f00702475
commit 315d5e32bf
3 changed files with 42 additions and 17 deletions
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7
frontends/verific/verific.cc
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@ -1297,7 +1297,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se
// ==================================================================
VerificClocking::VerificClocking(VerificImporter *importer, Net *net)
VerificClocking::VerificClocking(VerificImporter *importer, Net *net, bool sva_at_only)
{
module = importer->module;
@ -1320,6 +1320,11 @@ VerificClocking::VerificClocking(VerificImporter *importer, Net *net)
body_net = body_inst->GetInput2();
}
}
else
{
if (sva_at_only)
return;
}
if (inst != nullptr && inst->Type() == PRIM_SVA_POSEDGE)
{