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verilog: save and restore overwritten macro arguments

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Zachary Snow 2021-07-15 10:36:50 -04:00 • committed by Zachary Snow
parent a055145b95
commit 3156226233
4 changed files with 54 additions and 4 deletions
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21
tests/verilog/macro_arg_tromp.sv Normal file
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// Taken from: https://github.com/YosysHQ/yosys/issues/2867
`define MIN(x, y) ((x) < (y) ? (x) : (y))
`define CEIL_DIV(x, y) (((x) / (y)) + `MIN((x) % (y), 1))
module pad_msg1 (input logic [`MIN(512*`CEIL_DIV(64, 512), 64)-1:0] x,
output logic [`MIN(512*`CEIL_DIV(64, 512), 64)-1:0] y);
assign y[63:0] = x;
endmodule
module pad_msg2 (input logic [((512*`CEIL_DIV(64, 512)) < (64) ? (512*`CEIL_DIV(64,512)) : (64))-1:0] x,
output logic [((512*`CEIL_DIV(64, 512)) < (64) ? (512*`CEIL_DIV(64,512)) : (64))-1:0] y);
assign y[63:0] = x;
endmodule
module top(...);
`define add(x) x +
input [3:0] A;
output [3:0] B;
assign B = `add(`add(3)A)A;
endmodule

2
tests/verilog/macro_arg_tromp.ys Normal file
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logger -expect-no-warnings
read_verilog -sv macro_arg_tromp.sv