From 314d01b35f1310a9c864ad63f9b0cd7b1f131e57 Mon Sep 17 00:00:00 2001
From: abhinavputhran <aputhran@andrew.cmu.edu>
Date: Sun, 8 Mar 2026 20:14:03 -0400
Subject: [PATCH] changed rtlil to verilog. setundef_selection_ff stays rtlil
 because we use specific cell names if write in verilog yosys assign name that
 can change

---
 tests/various/setundef_selection.ys          | 2 +-
 tests/various/setundef_selection_undriven.il | 4 ----
 tests/various/setundef_selection_undriven.v  | 4 ++++
 3 files changed, 5 insertions(+), 5 deletions(-)
 delete mode 100644 tests/various/setundef_selection_undriven.il
 create mode 100644 tests/various/setundef_selection_undriven.v

diff --git a/tests/various/setundef_selection.ys b/tests/various/setundef_selection.ys
index 64713a742..c49cc06da 100644
--- a/tests/various/setundef_selection.ys
+++ b/tests/various/setundef_selection.ys
@@ -11,7 +11,7 @@ sat -enable_undef -prove b 0 -falsify
 design -reset
 
 # Test that setundef -undriven -zero respects wire selection
-read_rtlil setundef_selection_undriven.il
+read_verilog setundef_selection_undriven.v
 setundef -undriven -zero w:b
 sat -prove b 0
 sat -enable_undef -prove a 0 -falsify
diff --git a/tests/various/setundef_selection_undriven.il b/tests/various/setundef_selection_undriven.il
deleted file mode 100644
index f77809eb2..000000000
--- a/tests/various/setundef_selection_undriven.il
+++ /dev/null
@@ -1,4 +0,0 @@
-module \test
-  wire output 1 \a
-  wire output 2 \b
-end
diff --git a/tests/various/setundef_selection_undriven.v b/tests/various/setundef_selection_undriven.v
new file mode 100644
index 000000000..1fe5d585a
--- /dev/null
+++ b/tests/various/setundef_selection_undriven.v
@@ -0,0 +1,4 @@
+module test;
+    wire a;
+    wire b;
+endmodule