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Added adff2dff.v (for techmap -share_map)

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This commit is contained in:
Clifford Wolf 2014-08-07 16:14:38 +02:00
parent d259abbda2
commit 312ee00c9e
2 changed files with 32 additions and 1 deletions
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6
techlibs/common/Makefile.inc
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@ -5,7 +5,7 @@ techlibs/common/blackbox.v: techlibs/common/blackbox.sed techlibs/common/simlib.
$(P) cat techlibs/common/simlib.v techlibs/common/simcells.v | $(SED) -rf techlibs/common/blackbox.sed > techlibs/common/blackbox.v.new
$(Q) mv techlibs/common/blackbox.v.new techlibs/common/blackbox.v
EXTRA_TARGETS += share/simlib.v share/simcells.v share/techmap.v share/blackbox.v share/pmux2mux.v
EXTRA_TARGETS += share/simlib.v share/simcells.v share/techmap.v share/blackbox.v share/pmux2mux.v share/adff2dff.v
share/simlib.v: techlibs/common/simlib.v
$(P) mkdir -p share
@ -27,3 +27,7 @@ share/pmux2mux.v: techlibs/common/pmux2mux.v
$(P) mkdir -p share
$(Q) cp techlibs/common/pmux2mux.v share/pmux2mux.v
share/adff2dff.v: techlibs/common/adff2dff.v
$(P) mkdir -p share
$(Q) cp techlibs/common/adff2dff.v share/adff2dff.v

27
techlibs/common/adff2dff.v Normal file
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@ -0,0 +1,27 @@
(* techmap_celltype = "$adff" *)
module adff2dff (CLK, ARST, D, Q);
parameter WIDTH = 1;
parameter CLK_POLARITY = 1;
parameter ARST_POLARITY = 1;
parameter ARST_VALUE = 0;
input CLK, ARST;
input [WIDTH-1:0] D;
output reg [WIDTH-1:0] Q;
wire reg [WIDTH-1:0] NEXT_Q;
wire [1023:0] _TECHMAP_DO_ = "proc;;";
always @*
if (ARST == ARST_POLARITY)
NEXT_Q <= ARST_VALUE;
else
NEXT_Q <= D;
if (CLK_POLARITY)
always @(posedge CLK)
Q <= NEXT_Q;
else
always @(negedge CLK)
Q <= NEXT_Q;
endmodule