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Cleanup
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parent
f60cd4ff9b
commit
30f1204721
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@ -521,7 +521,7 @@ struct XAigerWriter
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for (int i = 0; i < GetSize(wire); i++)
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for (int i = 0; i < GetSize(wire); i++)
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{
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{
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if (aig_map.count(sig[i]) == 0 || sig[i].wire == nullptr)
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if (aig_map.count(sig[i]) == 0 /*|| sig[i].wire == nullptr*/)
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continue;
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continue;
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int a = aig_map.at(sig[i]);
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int a = aig_map.at(sig[i]);
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@ -529,13 +529,14 @@ struct XAigerWriter
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if (verbose_map)
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if (verbose_map)
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wire_lines[a] += stringf("wire %d %d %s\n", a, i, log_id(wire));
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wire_lines[a] += stringf("wire %d %d %s\n", a, i, log_id(wire));
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if (wire->port_input || ci_bits.count(RTLIL::SigBit{wire, i})) {
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RTLIL::SigBit b(wire, i);
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if (wire->port_input || ci_bits.count(b)) {
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log_assert((a & 1) == 0);
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log_assert((a & 1) == 0);
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input_lines[a] += stringf("input %d %d %s\n", (a >> 1)-1, i, log_id(wire));
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input_lines[a] += stringf("input %d %d %s\n", (a >> 1)-1, i, log_id(wire));
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}
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}
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if (output_bits.count(RTLIL::SigBit{wire, i}) || co_bits.count(RTLIL::SigBit{wire, i})) {
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if (output_bits.count(b) || co_bits.count(b)) {
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int o = ordered_outputs.at(sig[i]);
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int o = ordered_outputs.at(b);
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output_lines[o] += stringf("output %d %d %s\n", o, i, log_id(wire));
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output_lines[o] += stringf("output %d %d %s\n", o, i, log_id(wire));
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}
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}
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