Merge pull request #5982 from YosysHQ/cleanup

File cleanup

.github/ISSUE_TEMPLATE/config.yml

@@ -5,4 +5,3 @@ contact_links:
   - name: IRC Channel
     url: https://web.libera.chat/#yosys
     about: "#yosys on irc.libera.chat"
-

.github/ISSUE_TEMPLATE/feature_request.yml

@@ -22,4 +22,3 @@ body:
       description: "A clear and detailed description of the feature."
     validations:
       required: true
-

.pre-commit-config.yaml

@@ -0,0 +1,30 @@
+# To use:
+#
+#     pre-commit run -a
+#
+# Or:
+#
+#     pre-commit install  # (runs every time you commit in git)
+#
+# To update this file:
+#
+#     pre-commit autoupdate
+#
+# See https://github.com/pre-commit/pre-commit
+
+exclude: ^libs/
+
+repos:
+- repo: https://github.com/pre-commit/pre-commit-hooks
+  rev: v6.0.0
+  hooks:
+  - id: check-case-conflict
+  - id: check-executables-have-shebangs
+  - id: check-illegal-windows-names
+  - id: check-yaml
+    args: [--allow-multiple-documents]
+  - id: end-of-file-fixer
+  - id: fix-byte-order-marker
+  - id: mixed-line-ending
+    args: [--fix,lf]
+  - id: trailing-whitespace

CHANGELOG

@@ -1802,4 +1802,3 @@ Yosys 0.1.0 .. Yosys 0.2.0
      - Added "design -stash/-copy-from/-copy-to"
      - Added "copy" command
      - Added "splice" command
-

README.md

@@ -303,4 +303,3 @@ DOCS (e.g.)
 This will build/rebuild yosys as necessary before generating the website
 documentation from the yosys help commands.  To build for pdf instead of html,
 use the `docs-latexpdf` target.
-

backends/btor/test_cells.sh

@@ -27,4 +27,3 @@ for fn in test_*.il; do
 done
 
 echo "OK."
-

backends/edif/runtest.py

@@ -118,4 +118,3 @@ os.system("set -x; ./test_gold > test_gold.out")
 os.system("set -x; ./test_gate > test_gate.out")
 
 os.system("set -x; md5sum test_gold.out test_gate.out")
-

backends/simplec/test00_uut.v

@@ -11,4 +11,3 @@ endmodule
 module unit_y(input [31:0] a, b, c, output [31:0] y);
   assign y = a & (b | c);
 endmodule
-

backends/smt2/test_cells.sh

@@ -52,4 +52,3 @@ echo ""
 echo "  All tests passed."
 echo ""
 exit 0
-

backends/smv/test_cells.sh

@@ -30,4 +30,3 @@ for fn in test_*.il; do
 done
 
 grep '^-- invariant .* is false' *.out || echo 'All OK.'
-

docs/source/appendix/env_vars.rst

@@ -29,4 +29,3 @@ Yosys environment variables
 ``YOSYS_ABORT_ON_LOG_ERROR``
    Can be used for debugging Yosys internals.  Setting it to 1 causes abort() to
    be called when Yosys terminates with an error message.
-

docs/source/code_examples/intro/mycells.v

@@ -20,4 +20,3 @@ output reg Q;
 always @(posedge C)
 	Q <= D;
 endmodule
-

docs/source/code_examples/macc/Makefile

@@ -16,4 +16,3 @@ macc_xilinx_xmap.dot: macc_xilinx_*.v macc_xilinx_test.ys
 .PHONY: clean
 clean:
 	@rm -f *.dot
-

docs/source/code_examples/macc/macc_xilinx_test.ys

@@ -50,4 +50,3 @@ show -prefix macc_xilinx_test2e -format dot -notitle test2
 
 design -load __macc_xilinx_xmap
 show -prefix macc_xilinx_xmap -format dot -notitle
-

docs/source/code_examples/macro_commands/synth_ice40.ys

@@ -88,4 +88,3 @@ check:
     stat
     check -noinit
     blackbox =A:whitebox
-        

docs/source/code_examples/opt/opt_merge.ys

@@ -15,4 +15,3 @@ opt_merge after
 clean
 
 show -format dot -prefix opt_merge_full -notitle -color cornflowerblue uut
-

docs/source/code_examples/opt/opt_muxtree.ys

@@ -14,4 +14,3 @@ opt_muxtree after
 clean
 
 show -format dot -prefix opt_muxtree_full -notitle -color cornflowerblue uut
-

docs/source/code_examples/scrambler/scrambler.ys

@@ -19,4 +19,3 @@ eval -set in 1 -show out
 eval -set in 270369 -show out
 
 sat -set out 632435482
-

docs/source/code_examples/synth_flow/Makefile

@@ -17,4 +17,3 @@ examples:
 .PHONY: clean
 clean:
 	@rm -f *.dot
-

docs/source/using_yosys/synthesis/abc.rst

@@ -178,4 +178,3 @@ of carry chains and DSPs, it avoids optimising for a path that isn't the actual
 critical path, while the generally-longer paths result in ABC9 being able to
 reduce design area by mapping other logic to slower cells with greater logic
 density.
-

docs/source/using_yosys/synthesis/index.rst

@@ -31,4 +31,3 @@ for commands such as `abc`\ /`abc9`, `simplemap`, `dfflegalize`, and
    extract
    abc
    cell_libs
-

docs/source/using_yosys/synthesis/memory.rst

@@ -787,4 +787,3 @@ Asynchronous writes
 	end
 
 	assign read_data = mem[read_addr];
-

docs/source/yosys_internals/extending_yosys/index.rst

@@ -14,4 +14,3 @@ of interest for developers looking to customise Yosys builds.
    advanced_bugpoint
    contributing
    test_suites
-

docs/source/yosys_internals/extending_yosys/test_suites.rst

@@ -194,4 +194,3 @@ compiler versions.  For up to date information, including OS versions, refer to
    .. code-block:: console
 
       cmake --build build --target test-unit
-

docs/source/yosys_internals/flow/index.rst

@@ -16,4 +16,3 @@ These scripts contain three types of commands:
 	overview
 	control_and_data
 	verilog_frontend
-

docs/source/yosys_internals/formats/index.rst

@@ -56,4 +56,3 @@ constructs must be called from the synthesis script first.
 .. [1]
    In Yosys the term pass is only used to refer to commands that operate on the
    RTLIL data structure.
-

examples/basys3/README

@@ -16,4 +16,3 @@ Programming board:
 
 All of the above:
   bash run.sh
-

examples/basys3/example.xdc

@@ -21,4 +21,3 @@ create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports CLK
 
 set_property CONFIG_VOLTAGE 3.3 [current_design]
 set_property CFGBVS VCCO [current_design]
-

examples/cmos/README

@@ -10,4 +10,3 @@ Each test bench can be run separately by either running:
 
 The later case also includes pure verilog simulation using the iverilog
 and gtkwave for comparison.
-

examples/cmos/cmos_cells.sp

@@ -36,4 +36,3 @@ X1 nC D t DLATCH
 X2 C t Q DLATCH
 X3 C nC NOT
 .ENDS DFF
-

examples/cmos/cmos_cells.v

@@ -41,4 +41,3 @@ always @(posedge C, posedge S, posedge R)
 	else
 		Q <= D;
 endmodule
-

examples/cmos/cmos_cells_digital.sp

@@ -28,4 +28,3 @@ Alatch D E null null Q nQ latch1
 .model dff1 d_dff
 Adff D C null null Q nQ dff1
 .ENDS DFF
-

examples/cmos/counter_digital.ys

@@ -13,4 +13,3 @@ abc -liberty cmos_cells.lib;;
 
 write_verilog synth.v
 write_spice -neg 0s -pos 1s synth.sp
-

examples/cmos/testbench.sh

@@ -4,4 +4,3 @@ set -ex
 
 ../../yosys counter.ys
 ngspice testbench.sp
-

examples/cmos/testbench_digital.sh

@@ -12,4 +12,3 @@ iverilog -o counter_tb counter.v counter_tb.v
 
 # requires ngspice with xspice support enabled:
 ngspice testbench_digital.sp
-

examples/cxx-api/demomain.cc

@@ -19,4 +19,3 @@ int main()
 	Yosys::yosys_shutdown();
 	return 0;
 }
-

examples/gowin/README

@@ -14,4 +14,3 @@ gowinTool_linux directory
 
 3.) edit gowinTool_linux/bin/gwlicense.ini. Set lic="..." to
 the full path to the license file.
-

examples/intel/MAX10/runme_postsynth

@@ -2,4 +2,3 @@
 
 iverilog -D POST_IMPL -o verif_post -s tb_top tb_top.v top.vqm $(yosys-config --datdir/altera_intel/max10/cells_comb_max10.v)
 vvp -N verif_post
-

examples/intel/asicworld_lfsr/runme_postsynth

@@ -2,4 +2,3 @@
 
 iverilog -D POST_IMPL -o verif_post -s tb lfsr_updown_tb.v top.vqm $(yosys-config --datdir/altera_intel/max10/cells_comb_max10.v)
 vvp -N verif_post
-

examples/osu035/Makefile

@@ -10,4 +10,3 @@ osu035_stdcells.lib:
 clean:
 	rm -f osu035_stdcells.lib
 	rm -f example.yslog example.edif
-

examples/smtbmc/Makefile

@@ -74,4 +74,3 @@ clean:
 	rm -f glift_mux.ys
 
 .PHONY: demo1 demo2 demo3 demo4 demo5 demo6 demo7 demo8 demo9 clean
-

examples/smtbmc/demo9.v

@@ -10,4 +10,3 @@ module demo9;
 		cover(1);
 	end
 endmodule
-

frontends/ast/dpicall.cc

@@ -161,4 +161,3 @@ std::unique_ptr<AST::AstNode> AST::dpi_call(AstSrcLocType, const std::string&, c
 YOSYS_NAMESPACE_END
 
 #endif /* YOSYS_ENABLE_LIBFFI */
-

frontends/blif/blifparse.cc

@@ -691,4 +691,3 @@ struct BlifFrontend : public Frontend {
 } BlifFrontend;
 
 YOSYS_NAMESPACE_END
-

frontends/liberty/liberty.cc

@@ -836,5 +836,3 @@ skip_cell:;
 } LibertyFrontend;
 
 YOSYS_NAMESPACE_END
-
-

frontends/verific/README

@@ -34,4 +34,3 @@ should be something like this:
 	SBY [example] summary: engine_0 (smtbmc yices) returned PASS for induction
 	SBY [example] summary: successful proof by k-induction.
 	SBY [example] DONE (PASS, rc=0)
-

frontends/verilog/verilog_lexer.l

@@ -713,4 +713,3 @@ import[ \t\r\n]+\"(DPI|DPI-C)\"[ \t\r\n]+function[ \t\r\n]+ {
 <*>. { BEGIN(0); return char_tok(*YYText(), out_loc); }
 
 %%
-

kernel/calc.cc

@@ -712,4 +712,3 @@ RTLIL::Const RTLIL::const_bwmux(const RTLIL::Const &arg1, const RTLIL::Const &ar
 }
 
 YOSYS_NAMESPACE_END
-

kernel/cellhelp.py

@@ -97,4 +97,3 @@ for line in fileinput.input():
         print(simHelper)
         # new
         simHelper = SimHelper()
-

kernel/json.cc

@@ -169,4 +169,3 @@ void PrettyJson::entry_json(const char *name, const Json &value)
     this->name(name);
     this->value(value);
 }
-

passes/cmds/design.cc

@@ -401,4 +401,3 @@ struct DesignPass : public Pass {
 } DesignPass;
 
 YOSYS_NAMESPACE_END
-

passes/opt/opt_lut_ins.cc

@@ -282,4 +282,3 @@ struct OptLutInsPass : public Pass {
 } OptLutInsPass;
 
 PRIVATE_NAMESPACE_END
-

passes/opt/opt_mem_feedback.cc

@@ -347,4 +347,3 @@ struct OptMemFeedbackPass : public Pass {
 } OptMemFeedbackPass;
 
 PRIVATE_NAMESPACE_END
-

passes/opt/opt_mem_priority.cc

@@ -106,4 +106,3 @@ struct OptMemPriorityPass : public Pass {
 } OptMemPriorityPass;
 
 PRIVATE_NAMESPACE_END
-

passes/opt/wreduce.cc

@@ -650,4 +650,3 @@ struct WreducePass : public Pass {
 } WreducePass;
 
 PRIVATE_NAMESPACE_END
-

passes/proc/proc_memwr.cc

@@ -117,4 +117,3 @@ struct ProcMemWrPass : public Pass {
 } ProcMemWrPass;
 
 PRIVATE_NAMESPACE_END
-

passes/sat/example.v

@@ -82,4 +82,3 @@ always @(posedge clk)
 assign y = counter == 12;
 
 endmodule
-

passes/sat/example.ys

@@ -11,4 +11,3 @@ sat -show rst,counter -set-at 3 y 1'b1 -seq 4 example004
 
 sat -prove y 1'b0 -show rst,counter,y -ignore_unknown_cells example004
 sat -prove y 1'b0 -tempinduct -show rst,counter,y -set-at 1 rst 1'b1 -seq 1 example004
-

passes/techmap/filterlib.cc

@@ -1,4 +1,3 @@
 
 #define FILTERLIB
 #include "libparse.cc"
-

passes/techmap/libparse.cc

@@ -1286,4 +1286,3 @@ int main(int argc, char **argv)
 }
 
 #endif
-

passes/tests/test_autotb.cc

@@ -389,4 +389,3 @@ struct TestAutotbBackend : public Backend {
 } TestAutotbBackend;
 
 PRIVATE_NAMESPACE_END
-

techlibs/achronix/speedster22i/cells_map.v

@@ -70,4 +70,3 @@ module  \$_DFF_P_ (input D, C, output Q);
    DFF _TECHMAP_REPLACE_
      (.q(Q), .d(D), .ck(C));
 endmodule
-

techlibs/achronix/speedster22i/cells_sim.v

@@ -74,6 +74,3 @@ module DFF (output reg q,
      q <= d;
 
 endmodule
-
-
-

techlibs/analogdevices/arith_map.v

@@ -170,4 +170,3 @@ module _80_analogdevices_alu (A, B, CI, BI, X, Y, CO);
 
 	assign X = S;
 endmodule
-

techlibs/analogdevices/ff_map.v

@@ -60,4 +60,3 @@ module  \$_SDFFE_PP1P_ (input D, C, E, R, output Q);
 endmodule
 
 `endif
-

techlibs/analogdevices/lut_map.v

@@ -76,4 +76,3 @@ module \$lut (A, Y);
 endmodule
 
 `endif
-

techlibs/fabulous/arith_map.v

@@ -62,4 +62,3 @@ assign X = AA ^ BB;
 
 endmodule
 `endif
-

techlibs/fabulous/io_map.v

@@ -5,4 +5,3 @@ endmodule
 module \$__FABULOUS_OBUF (output PAD, input I);
 	IO_1_bidirectional_frame_config_pass _TECHMAP_REPLACE_ (.PAD(PAD), .I(I), .T(1'b0));
 endmodule
-

techlibs/gatemate/gatemate_foldinv.cc

@@ -216,4 +216,3 @@ struct GatemateFoldInvPass : public Pass {
 } GatemateFoldInvPass;
 
 PRIVATE_NAMESPACE_END
-

techlibs/gowin/adc.v

@@ -257,4 +257,3 @@ module ADCA (
   parameter CSR_OFFSET           = -12'd1180;  // Parameter 2, signed number, temperature mode - 1560~- 760, typical value - 1180; Voltage mode - 410~410, typical value 0
 
 endmodule
-

techlibs/gowin/arith_map.v

@@ -64,4 +64,3 @@ module _80_gw1n_alu(A, B, CI, BI, X, Y, CO);
    end endgenerate
    assign X = AA ^ BB ^ {Y_WIDTH{BI}};
 endmodule
-

techlibs/gowin/cells_sim.v

@@ -2151,5 +2151,3 @@ module EMCU (
 
  );
 endmodule
-
-

techlibs/gowin/cells_xtra.py

@@ -103,4 +103,3 @@ if __name__ == '__main__':
                     with open(f'adc.v', 'r') as fin:
                         for l in fin:
                             fout.write(l);
-

techlibs/gowin/cells_xtra_gw5a.v

@@ -2787,4 +2787,3 @@ module ADCA (
   parameter CSR_OFFSET           = -12'd1180;  // Parameter 2, signed number, temperature mode - 1560~- 760, typical value - 1180; Voltage mode - 410~410, typical value 0
 
 endmodule
-

techlibs/ice40/arith_map.v

@@ -72,4 +72,3 @@ module _80_ice40_alu (A, B, CI, BI, X, Y, CO);
 
 	assign X = AA ^ BB;
 endmodule
-

techlibs/ice40/tests/test_bram.sh

@@ -16,4 +16,3 @@ for dbits in 2 4 8 16 24 32; do
 	if grep -H ERROR ${id}_tb.txt; then false; fi
 done; done
 echo OK
-

techlibs/intel/common/brams_map_m9k.v

@@ -90,4 +90,3 @@ module \$__M9K_ALTSYNCRAM_SINGLEPORT_FULL (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1A
                                       .addressstall_b(1'b0));
 
 endmodule
-

techlibs/intel/cyclone10lp/cells_map.v

@@ -71,5 +71,3 @@ module \$lut (A, Y);
    endgenerate
 
 endmodule
-
-

techlibs/intel/cycloneiv/cells_map.v

@@ -55,5 +55,3 @@ module \$lut (A, Y);
 	   wire _TECHMAP_FAIL_ = 1;
    endgenerate
 endmodule //
-
-

techlibs/intel/cycloneiv/cells_sim.v

@@ -295,5 +295,3 @@ module cycloneiv_pll
    output                                   icdrclk;
 
 endmodule // cycloneive_pll
-
-

techlibs/intel/cycloneive/cells_map.v

@@ -71,5 +71,3 @@ module \$lut (A, Y);
    endgenerate
 
 endmodule
-
-

techlibs/intel/max10/cells_map.v

@@ -55,5 +55,3 @@ module \$lut (A, Y);
 	   wire _TECHMAP_FAIL_ = 1;
    endgenerate
 endmodule //
-
-

techlibs/intel/max10/dsp_map.v

@@ -70,4 +70,3 @@ module \$__MUL9X9 (input [8:0] A, input [8:0] B, output [17:0] Y);
 		.dataout (Y)
 	);
 endmodule
-

techlibs/lattice/cells_bb_ecp5.v

@@ -2030,4 +2030,3 @@ module DCUA(CH0_HDINP, CH1_HDINP, CH0_HDINN, CH1_HDINN, D_TXBIT_CLKP_FROM_ND, D_
     input D_REFCLKI;
     output D_FFS_PLOL;
 endmodule
-

techlibs/lattice/cells_bb_nexus.v

@@ -10589,4 +10589,3 @@ module PCLKDIVSP(CLKIN, CLKOUT, LSRPDIV);
     output CLKOUT;
     input LSRPDIV;
 endmodule
-

techlibs/lattice/cells_bb_xo2.v

@@ -579,4 +579,3 @@ endmodule
 module TSALL(TSALL);
     input TSALL;
 endmodule
-

techlibs/lattice/cells_bb_xo3.v

@@ -579,4 +579,3 @@ endmodule
 module TSALL(TSALL);
     input TSALL;
 endmodule
-

techlibs/lattice/cells_bb_xo3d.v

@@ -580,4 +580,3 @@ endmodule
 module TSALL(TSALL);
     input TSALL;
 endmodule
-

techlibs/microchip/arith_map.v

@@ -102,4 +102,3 @@ module \$__SF2_ALU (A, B, CI, BI, X, Y, CO);
 		);
 	end endgenerate
 endmodule
-

techlibs/microchip/cells_map.v

@@ -101,4 +101,3 @@ module \$lut (A, Y);
 	endgenerate
 endmodule
 `endif
-

techlibs/microchip/uSRAM_map.v

@@ -123,4 +123,3 @@ RAM64x12 #(
 );
 
 endmodule
-

techlibs/nanoxplore/cells_bb_l.v

@@ -2153,4 +2153,3 @@ module NX_IOM_CONTROL_L(RTCK1, RRCK1, WTCK1, WRCK1, RTCK2, RRCK2, WTCK2, WRCK2,
     parameter sel_clkw_rx1 = 2'b00;
     parameter sel_clkw_rx2 = 2'b00;
 endmodule
-