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minor cleanup and fixes

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This commit is contained in:
Artur Swiderski 2020-10-24 00:02:05 +02:00
parent 41f83c19fd
commit 309689da5b
11 changed files with 76 additions and 355 deletions
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3
techlibs/intel_le/Makefile.inc
View file

@ -10,15 +10,12 @@ $(eval $(call add_share_file,share/intel_le/common,techlibs/intel_le/common/le_s
$(eval $(call add_share_file,share/intel_le/common,techlibs/intel_le/common/arith_le_map.v)) $(eval $(call add_share_file,share/intel_le/common,techlibs/intel_le/common/arith_le_map.v))
$(eval $(call add_share_file,share/intel_le/common,techlibs/intel_le/common/dff_map.v)) $(eval $(call add_share_file,share/intel_le/common,techlibs/intel_le/common/dff_map.v))
$(eval $(call add_share_file,share/intel_le/common,techlibs/intel_le/common/dff_sim.v)) $(eval $(call add_share_file,share/intel_le/common,techlibs/intel_le/common/dff_sim.v))
$(eval $(call add_share_file,share/intel_le/common,techlibs/intel_le/common/dsp_sim.v))
$(eval $(call add_share_file,share/intel_le/common,techlibs/intel_le/common/dsp_map.v))
$(eval $(call add_share_file,share/intel_le/common,techlibs/intel_le/common/mem_sim.v)) $(eval $(call add_share_file,share/intel_le/common,techlibs/intel_le/common/mem_sim.v))
$(eval $(call add_share_file,share/intel_le/cycloneiv,techlibs/intel_le/cycloneiv/cells_sim.v)) $(eval $(call add_share_file,share/intel_le/cycloneiv,techlibs/intel_le/cycloneiv/cells_sim.v))
# RAM # RAM
$(eval $(call add_share_file,share/intel_le/common,techlibs/intel_le/common/bram_m9k.txt)) $(eval $(call add_share_file,share/intel_le/common,techlibs/intel_le/common/bram_m9k.txt))
$(eval $(call add_share_file,share/intel_le/common,techlibs/intel_le/common/bram_m20k_map.v))
# Miscellaneous # Miscellaneous
$(eval $(call add_share_file,share/intel_le/common,techlibs/intel_le/common/megafunction_bb.v)) $(eval $(call add_share_file,share/intel_le/common,techlibs/intel_le/common/megafunction_bb.v))

25
techlibs/intel_le/common/arith_le_map.v
View file

@ -30,21 +30,21 @@ wire [Y_WIDTH-1:0] AA = A_buf;
wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf; wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;
(* force_downto *) (* force_downto *)
wire [Y_WIDTH-1:0] BX = B_buf; wire [Y_WIDTH-1:0] BX = B_buf;
wire [Y_WIDTH-1:0] BSUM; wire [Y_WIDTH-1:0] BTOADDER;
wire [Y_WIDTH:0] LE_CARRY; wire [Y_WIDTH:0] LE_CARRY;
// Start of carry chain // Start of carry chain
generate generate
if (_TECHMAP_CONSTMSK_CI_ == 1) begin if (_TECHMAP_CONSTMSK_CI_ == 1) begin
assign ALM_CARRY[0] = _TECHMAP_CONSTVAL_CI_; assign LE_CARRY[0] = _TECHMAP_CONSTVAL_CI_;
end else begin end else begin
MISTRAL_ALUT_ARITH #( MISTRAL_ALUT_ARITH #(
.LUT0(16'b1010_1010_1010_1010), // Q = A .LUT(16'b1010_1010_1010_1010), // Q = A
.LUT1(16'b0000_0000_0000_0000), // Q = 0 (LUT1's input to the adder is inverted)
) alm_start ( ) alm_start (
.A(CI), .B(1'b1), .C(1'b1), .D0(1'b1), .D1(1'b1), .A(CI), .B(1'b1), .C(1'b1), .D0(1'b1), .D1(1'b1),
.CI(1'b0), .CI(1'b0),
.CO(ALM_CARRY[0]) .SO(),
.CO(LE_CARRY[0])
); );
end end
endgenerate endgenerate
@ -54,25 +54,24 @@ genvar i;
generate for (i = 0; i < Y_WIDTH; i = i + 1) begin:slice generate for (i = 0; i < Y_WIDTH; i = i + 1) begin:slice
// TODO: mwk suggests that a pass could merge pre-adder logic into this. // TODO: mwk suggests that a pass could merge pre-adder logic into this.
MISTRAL_ALUT_ARITH #( MISTRAL_ALUT_ARITH #(
.LUT0(16'b0110_0110_0110_0110) // Q = A ? ~B : B .LUT(16'b0110_0110_0110_0110) // Q = A ? ~B : B
) alm_i ( ) alm_i (
.A(BI), .B(BX[i]), .C(1'b0), .D(1'b0), .A(BI), .B(BX[i]), .C(1'b0), .D(1'b0),
.CI(1'b0), .CI(1'b0),
.SO(BSUM[i]), .SO(BTOADDER[i]),
.CO() .CO()
); );
MISTRAL_ALUT_ARITH #( MISTRAL_ALUT_ARITH #(
.LUT0(16'b1010_1010_1010_1010), // SUM = A xor B xor CI .LUT(16'b1010_1010_1010_1010), // SUM = A xor B xor CI
// CARRYi+1 = A and B or A and CI or B and CI // CARRYi+1 = A and B or A and CI or B and CI
.sum_lutc_input("cin") .sum_lutc_input("cin")
) alm_start ( ) alm_start (
.A(AA[i]), .B(BX[i]), .C(1'b1), .D(1'b1), .A(AA[i]), .B(BTOADDER[i]), .C(1'b1), .D(1'b1),
.CI(LE_CARRY), .CI(LE_CARRY[i]),
.SO(Y[i]), .SO(Y[i]),
.CO(ALM_CARRY[i+1]) .CO(LE_CARRY[i+1])
); );
// ALM carry chain is not directly accessible, so calculate the carry through soft logic if really needed.
assign CO[i] = (AA[i] && BB[i]) || ((Y[i] ^ AA[i] ^ BB[i]) && (AA[i] || BB[i]));
end endgenerate end endgenerate
assign X = AA ^ BB; assign X = AA ^ BB;

33
techlibs/intel_le/common/bram_m20k.txt
View file

@ -1,33 +0,0 @@
bram __MISTRAL_M20K_SDP
init 1 # TODO: Re-enable when I figure out how BRAM init works
abits 14 @D16384x1
dbits 1 @D16384x1
abits 13 @D8192x2
dbits 2 @D8192x2
abits 12 @D4096x4 @D4096x5
dbits 4 @D4096x4
dbits 5 @D4096x5
abits 11 @D2048x8 @D2048x10
dbits 8 @D2048x8
dbits 10 @D2048x10
abits 10 @D1024x16 @D1024x20
dbits 16 @D1024x16
dbits 20 @D1024x20
abits 9 @D512x32 @D512x40
dbits 32 @D512x32
dbits 40 @D512x40
groups 2
ports 1 1
wrmode 1 0
# read enable; write enable + byte enables (only for multiples of 8)
enable 1 1
transp 0 0
clocks 1 1
clkpol 1 1
endbram
match __MISTRAL_M20K_SDP
min efficiency 5
make_transp
endmatch

31
techlibs/intel_le/common/bram_m20k_map.v
View file

@ -1,31 +0,0 @@
module __MISTRAL_M20K_SDP(CLK1, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
parameter CFG_ABITS = 10;
parameter CFG_DBITS = 20;
parameter CFG_ENABLE_A = 1;
parameter CFG_ENABLE_B = 1;
input CLK1;
input [CFG_ABITS-1:0] A1ADDR, B1ADDR;
input [CFG_DBITS-1:0] A1DATA;
output [CFG_DBITS-1:0] B1DATA;
input [CFG_ENABLE_A-1:0] A1EN, B1EN;
altsyncram #(
.operation_mode("dual_port"),
.ram_block_type("m20k"),
.widthad_a(CFG_ABITS),
.width_a(CFG_DBITS),
.widthad_b(CFG_ABITS),
.width_b(CFG_DBITS),
) _TECHMAP_REPLACE_ (
.address_a(A1ADDR),
.data_a(A1DATA),
.wren_a(A1EN),
.address_b(B1ADDR),
.q_b(B1DATA),
.clock0(CLK1),
.clock1(CLK1)
);
endmodule

17
techlibs/intel_le/common/bram_m9k.txt
View file

@ -1,21 +1,20 @@
bram MISTRAL_M10K bram MISTRAL_M9K
init 0 # TODO: Re-enable when I figure out how BRAM init works init 0 # TODO: Re-enable when I figure out how BRAM init works
abits 13 @D8192x1 abits 13 @D8192x1
dbits 1 @D8192x1 dbits 1 @D8192x1
abits 12 @D4096x2 abits 12 @D4096x2
dbits 2 @D4096x2 dbits 2 @D4096x2
abits 11 @D2048x4 @D2048x5 abits 11 @D2048x4
dbits 4 @D2048x4 dbits 4 @D2048x4
dbits 5 @D2048x5 abits 10 @D1024x8 @D1024x9
abits 10 @D1024x8 @D1024x10
dbits 8 @D1024x8 dbits 8 @D1024x8
dbits 10 @D1024x10 dbits 9 @D1024x9
abits 9 @D512x16 @D512x20 abits 9 @D512x16 @D512x18
dbits 16 @D512x16 dbits 16 @D512x16
dbits 20 @D512x20 dbits 18 @D512x18
abits 8 @D256x32 @D256x40 abits 8 @D256x32 @D256x36
dbits 32 @D256x32 dbits 32 @D256x32
dbits 40 @D256x40 dbits 36 @D256x36
groups 2 groups 2
ports 1 1 ports 1 1
wrmode 1 0 wrmode 1 0

51
techlibs/intel_le/common/dsp_map.v
View file

@ -1,51 +0,0 @@
`default_nettype none
module __MUL27X27(A, B, Y);
parameter A_SIGNED = 1;
parameter B_SIGNED = 1;
parameter A_WIDTH = 27;
parameter B_WIDTH = 27;
parameter Y_WIDTH = 54;
input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y;
MISTRAL_MUL27X27 _TECHMAP_REPLACE_ (.A(A), .B(B), .Y(Y));
endmodule
module __MUL18X18(A, B, Y);
parameter A_SIGNED = 1;
parameter B_SIGNED = 1;
parameter A_WIDTH = 18;
parameter B_WIDTH = 18;
parameter Y_WIDTH = 36;
input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y;
MISTRAL_MUL18X18 _TECHMAP_REPLACE_ (.A(A), .B(B), .Y(Y));
endmodule
module __MUL9X9(A, B, Y);
parameter A_SIGNED = 1;
parameter B_SIGNED = 1;
parameter A_WIDTH = 9;
parameter B_WIDTH = 9;
parameter Y_WIDTH = 18;
input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y;
MISTRAL_MUL9X9 _TECHMAP_REPLACE_ (.A(A), .B(B), .Y(Y));
endmodule

83
techlibs/intel_le/common/dsp_sim.v
View file

@ -1,83 +0,0 @@
(* abc9_box *)
module MISTRAL_MUL27X27(input [26:0] A, input [26:0] B, output [53:0] Y);
parameter A_SIGNED = 1;
parameter B_SIGNED = 1;
// TODO: Cyclone 10 GX timings; the below are for Cyclone V
specify
(A *> Y) = 3732;
(B *> Y) = 3928;
endspecify
wire [53:0] A_, B_;
if (A_SIGNED)
assign A_ = $signed(A);
else
assign A_ = $unsigned(A);
if (B_SIGNED)
assign B_ = $signed(B);
else
assign B_ = $unsigned(B);
assign Y = A_ * B_;
endmodule
(* abc9_box *)
module MISTRAL_MUL18X18(input [17:0] A, input [17:0] B, output [35:0] Y);
parameter A_SIGNED = 1;
parameter B_SIGNED = 1;
// TODO: Cyclone 10 GX timings; the below are for Cyclone V
specify
(A *> Y) = 3180;
(B *> Y) = 3982;
endspecify
wire [35:0] A_, B_;
if (A_SIGNED)
assign A_ = $signed(A);
else
assign A_ = $unsigned(A);
if (B_SIGNED)
assign B_ = $signed(B);
else
assign B_ = $unsigned(B);
assign Y = A_ * B_;
endmodule
(* abc9_box *)
module MISTRAL_MUL9X9(input [8:0] A, input [8:0] B, output [17:0] Y);
parameter A_SIGNED = 1;
parameter B_SIGNED = 1;
// TODO: Cyclone 10 GX timings; the below are for Cyclone V
specify
(A *> Y) = 2818;
(B *> Y) = 3051;
endspecify
wire [17:0] A_, B_;
if (A_SIGNED)
assign A_ = $signed(A);
else
assign A_ = $unsigned(A);
if (B_SIGNED)
assign B_ = $signed(B);
else
assign B_ = $unsigned(B);
assign Y = A_ * B_;
endmodule

14
techlibs/intel_le/common/le_sim.v
View file

@ -231,32 +231,30 @@ assign Q = ~A;
endmodule endmodule
(* abc9_box, lib_whitebox *) (* abc9_box, lib_whitebox *)
module MISTRAL_ALUT_ARITH(input A, B, C, D, (* abc9_carry *) input CI, output , (* abc9_carry *) output CO); module MISTRAL_ALUT_ARITH(input A, B, C, D, (* abc9_carry *) input CI, output SO, (* abc9_carry *) output CO);
parameter LUT = 16'h0000; parameter LUT = 16'h0000;
parameter sum_lutc_input = "cin"; parameter sum_lutc_input = "cin";
`ifdef cycloneiv `ifdef cycloneiv
specify specify
(A => SO) = 1342; (A => SO) = 1342;
(B => SO) = 1323; (B => SO) = 1323;
(C => SO) = 927; (C => SO) = 927;
(D0 => SO) = 887; (D => SO) = 887;
(D1 => SO) = 785;
(CI => SO) = 368; (CI => SO) = 368;
(A => CO) = 1082; (A => CO) = 1082;
(B => CO) = 1062; (B => CO) = 1062;
(C => CO) = 813; (C => CO) = 813;
(D0 => CO) = 866; (D => CO) = 866;
(D1 => CO) = 1198;
(CI => CO) = 36; // Divided by 2 to account for there being two ALUT_ARITHs in an ALM) (CI => CO) = 36; // Divided by 2 to account for there being two ALUT_ARITHs in an ALM)
endspecify endspecify
`endif `endif
wire q0, q1; wire q0, q1;
assign q0 = LUT0 >> sum_lutc_input == "cin" : {D, CI, B, A},{D, C, B, A}; assign q0 = LUT >> sum_lutc_input == "cin" ? {D, CI, B, A}:{D, C, B, A};
assign q1 = LUT0 >> sum_lutc_input == "cin" : {'b0, CI, B, A},{'b0, C, B, A}; assign q1 = LUT >> sum_lutc_input == "cin" ? {'b1, CI, B, A}:{'b1, C, B, A};
assign SO = D ? q1 : q0; assign SO = D ? q1 : q0;

2
techlibs/intel_le/common/mem_sim.v
View file

@ -74,7 +74,7 @@ assign B1DATA = mem[B1ADDR];
endmodule endmodule
// The M10K // The M9K
// -------- // --------
// TODO // TODO

91
techlibs/intel_le/common/quartus_rename.v
View file

@ -3,11 +3,6 @@
`define MAC cycloneiv_mac `define MAC cycloneiv_mac
`define MLAB cycloneiv_mlab_cell `define MLAB cycloneiv_mlab_cell
`endif `endif
`ifdef cyclone10gx
`define LCELL cyclone10gx_lcell_comb
`define MAC cyclone10gx_mac
`define MLAB cyclone10gx_mlab_cell
`endif
module __MISTRAL_VCC(output Q); module __MISTRAL_VCC(output Q);
@ -30,20 +25,6 @@ dffeas #(.power_up("low"), .is_wysiwyg("true")) _TECHMAP_REPLACE_ (.d(DATAIN), .
endmodule endmodule
module MISTRAL_ALUT6(input A, B, C, D, E, F, output Q);
parameter [63:0] LUT = 64'h0000_0000_0000_0000;
`LCELL #(.lut_mask(LUT)) _TECHMAP_REPLACE_ (.dataa(A), .datab(B), .datac(C), .datad(D), .datae(E), .dataf(F), .combout(Q));
endmodule
module MISTRAL_ALUT5(input A, B, C, D, E, output Q);
parameter [31:0] LUT = 32'h0000_0000;
`LCELL #(.lut_mask({2{LUT}})) _TECHMAP_REPLACE_ (.dataa(A), .datab(B), .datac(C), .datad(D), .datae(E), .combout(Q));
endmodule
module MISTRAL_ALUT4(input A, B, C, D, output Q); module MISTRAL_ALUT4(input A, B, C, D, output Q);
@ -77,11 +58,10 @@ NOT _TECHMAP_REPLACE_ (.IN(A), .OUT(Q));
endmodule endmodule
module MISTRAL_ALUT_ARITH(input A, B, C, D0, D1, CI, output SO, CO); module MISTRAL_ALUT_ARITH(input A, B, C, D, CI, output SO, CO);
parameter LUT0 = 16'h0000; parameter LUT = 16'h0000;
parameter LUT1 = 16'h0000;
`LCELL #(.lut_mask({16'h0, LUT1, 16'h0, LUT0})) _TECHMAP_REPLACE_ (.dataa(A), .datab(B), .datac(C), .datad(D0), .dataf(D1), .cin(CI), .sumout(SO), .cout(CO)); `LCELL #(.lut_mask({16'h0, LUT})) _TECHMAP_REPLACE_ (.dataa(A), .datab(B), .datac(C), .datad(D), .cin(CI), .sumout(SO), .cout(CO));
endmodule endmodule
@ -125,7 +105,7 @@ parameter _TECHMAP_CELLNAME_ = "";
endmodule endmodule
module MISTRAL_M10K(A1ADDR, A1DATA, A1EN, CLK1, B1ADDR, B1DATA, B1EN); module MISTRAL_M9K(A1ADDR, A1DATA, A1EN, CLK1, B1ADDR, B1DATA, B1EN);
parameter CFG_ABITS = 10; parameter CFG_ABITS = 10;
parameter CFG_DBITS = 10; parameter CFG_DBITS = 10;
@ -137,7 +117,7 @@ input [CFG_DBITS-1:0] A1DATA;
input CLK1, A1EN, B1EN; input CLK1, A1EN, B1EN;
output [CFG_DBITS-1:0] B1DATA; output [CFG_DBITS-1:0] B1DATA;
// Much like the MLAB, the M10K has mem_init[01234] parameters which would let // Much like the MLAB, the M9K has mem_init[01234] parameters which would let
// you initialise the RAM cell via hex literals. If they were implemented. // you initialise the RAM cell via hex literals. If they were implemented.
cycloneiv_ram_block #( cycloneiv_ram_block #(
@ -172,64 +152,3 @@ cycloneiv_ram_block #(
endmodule endmodule
module MISTRAL_MUL27X27(input [26:0] A, B, output [53:0] Y);
parameter A_SIGNED = 1;
parameter B_SIGNED = 1;
`MAC #(
.ax_width(27),
.signed_max(A_SIGNED ? "true" : "false"),
.ay_scan_in_width(27),
.signed_may(B_SIGNED ? "true" : "false"),
.result_a_width(54),
.operation_mode("M27x27")
) _TECHMAP_REPLACE_ (
.ax(A),
.ay(B),
.resulta(Y)
);
endmodule
module MISTRAL_MUL18X18(input [17:0] A, B, output [35:0] Y);
parameter A_SIGNED = 1;
parameter B_SIGNED = 1;
`MAC #(
.ax_width(18),
.signed_max(A_SIGNED ? "true" : "false"),
.ay_scan_in_width(18),
.signed_may(B_SIGNED ? "true" : "false"),
.result_a_width(36),
.operation_mode("M18x18_FULL")
) _TECHMAP_REPLACE_ (
.ax(A),
.ay(B),
.resulta(Y)
);
endmodule
module MISTRAL_MUL9X9(input [8:0] A, B, output [17:0] Y);
parameter A_SIGNED = 1;
parameter B_SIGNED = 1;
`MAC #(
.ax_width(9),
.signed_max(A_SIGNED ? "true" : "false"),
.ay_scan_in_width(9),
.signed_may(B_SIGNED ? "true" : "false"),
.result_a_width(18),
.operation_mode("M9x9")
) _TECHMAP_REPLACE_ (
.ax(A),
.ay(B),
.resulta(Y)
);
endmodule

81
techlibs/intel_le/cycloneiv/cells_sim.v
View file

@ -1,4 +1,4 @@
/* /*
* yosys -- Yosys Open SYnthesis Suite * yosys -- Yosys Open SYnthesis Suite
* *
* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
@ -41,22 +41,23 @@ endmodule // cycloneiv_io_obuf
/* Altera Cyclone IV LUT Primitive */ /* Altera Cyclone IV LUT Primitive */
module cycloneiv_lcell_comb module cycloneiv_lcell_comb
(output combout, cout, (output combout, cout,
input dataa, datab, datac, datad, input dataa, datab, datac, datad, cin);
input datae, dataf, datag, cin);
parameter lut_mask = 16'hFFFF; parameter lut_mask = 16'hFFFF;
parameter dont_touch = "off"; parameter dont_touch = "off";
parameter lpm_type = "cycloneiv_lcell_comb"; parameter lpm_type = "cycloneiv_lcell_comb";
parameter sum_lutc_input = "datac";
// Internal variables reg cout_tmp;
reg combout_tmp;
reg [1:0] isum_lutc_input;
// Independent output for fragmented LUTs wire dataa_in;
wire output_0, output_1, output_2, output_3; wire datab_in;
// Extended mode uses mux to define the output wire datac_in;
wire mux_0, mux_1; wire datad_in;
// Input for hold the shared LUT mode value wire cin_in;
wire shared_lut_alm;
// Simulation model of 4-input LUT // Simulation model of 4-input LUT
function lut4; function lut4;
@ -73,35 +74,41 @@ module cycloneiv_lcell_comb
end end
endfunction // lut4 endfunction // lut4
// Simulation model of 5-input LUT
function lut5;
input [31:0] mask; // wp-01003.pdf, page 3: "a 5-LUT can be built with two 4-LUTs and a multiplexer.
input dataa, datab, datac, datad, datae;
reg upper_lut_value;
reg lower_lut_value;
begin
upper_lut_value = lut4(mask[31:16], dataa, datab, datac, datad);
lower_lut_value = lut4(mask[15:0], dataa, datab, datac, datad);
lut5 = (datae) ? upper_lut_value : lower_lut_value;
end
endfunction // lut5
// Simulation model of 6-input LUT initial
function lut6; begin
input [63:0] mask; if (sum_lutc_input == "datac")
input dataa, datab, datac, datad, datae, dataf; isum_lutc_input = 0;
reg upper_lut_value; else if (sum_lutc_input == "cin")
reg lower_lut_value; isum_lutc_input = 1;
reg out_0, out_1, out_2, out_3; else
begin begin
upper_lut_value = lut5(mask[63:32], dataa, datab, datac, datad, datae); $display ("Error: Invalid sum_lutc_input specified\n");
lower_lut_value = lut5(mask[31:0], dataa, datab, datac, datad, datae); $display ("Time: %0t Instance: %m", $time);
lut6 = (dataf) ? upper_lut_value : lower_lut_value; isum_lutc_input = 2;
end end
endfunction // lut6
assign {mask_a, mask_b, mask_c, mask_d} = {lut_mask[15:0], lut_mask[31:16], lut_mask[47:32], lut_mask[63:48]}; end
always @(datad_in or datac_in or datab_in or dataa_in or cin_in)
begin
if (isum_lutc_input == 0) // datac
begin
combout_tmp = lut4(lut_mask, dataa_in, datab_in,
datac_in, datad_in);
end
else if (isum_lutc_input == 1) // cin
begin
combout_tmp = lut4(lut_mask, dataa_in, datab_in,
cin_in, datad_in);
end
cout_tmp = lut4(lut_mask, dataa_in, datab_in, cin_in, 'b0);
end
and (combout, combout_tmp, 1'b1) ;
and (cout, cout_tmp, 1'b1) ;
endmodule // cycloneiv_lcell_comb endmodule // cycloneiv_lcell_comb