mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-10-10 01:41:59 +00:00
Code Activity

minor cleanup and fixes

Browse source
This commit is contained in:
Artur Swiderski 2020-10-24 00:02:05 +02:00
parent 41f83c19fd
commit 309689da5b
11 changed files with 76 additions and 355 deletions
Download patch file Download diff file Expand all files Collapse all files

25
techlibs/intel_le/common/arith_le_map.v
View file

@ -30,21 +30,21 @@ wire [Y_WIDTH-1:0] AA = A_buf;
wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;
(* force_downto *)
wire [Y_WIDTH-1:0] BX = B_buf;
wire [Y_WIDTH-1:0] BSUM;
wire [Y_WIDTH-1:0] BTOADDER;
wire [Y_WIDTH:0] LE_CARRY;
// Start of carry chain
generate
if (_TECHMAP_CONSTMSK_CI_ == 1) begin
assign ALM_CARRY[0] = _TECHMAP_CONSTVAL_CI_;
assign LE_CARRY[0] = _TECHMAP_CONSTVAL_CI_;
end else begin
MISTRAL_ALUT_ARITH #(
.LUT0(16'b1010_1010_1010_1010), // Q = A
.LUT1(16'b0000_0000_0000_0000), // Q = 0 (LUT1's input to the adder is inverted)
.LUT(16'b1010_1010_1010_1010), // Q = A
) alm_start (
.A(CI), .B(1'b1), .C(1'b1), .D0(1'b1), .D1(1'b1),
.CI(1'b0),
.CO(ALM_CARRY[0])
.SO(),
.CO(LE_CARRY[0])
);
end
endgenerate
@ -54,25 +54,24 @@ genvar i;
generate for (i = 0; i < Y_WIDTH; i = i + 1) begin:slice
// TODO: mwk suggests that a pass could merge pre-adder logic into this.
MISTRAL_ALUT_ARITH #(
.LUT0(16'b0110_0110_0110_0110) // Q = A ? ~B : B
.LUT(16'b0110_0110_0110_0110) // Q = A ? ~B : B
) alm_i (
.A(BI), .B(BX[i]), .C(1'b0), .D(1'b0),
.CI(1'b0),
.SO(BSUM[i]),
.SO(BTOADDER[i]),
.CO()
);
MISTRAL_ALUT_ARITH #(
.LUT0(16'b1010_1010_1010_1010), // SUM = A xor B xor CI
.LUT(16'b1010_1010_1010_1010), // SUM = A xor B xor CI
// CARRYi+1 = A and B or A and CI or B and CI
.sum_lutc_input("cin")
) alm_start (
.A(AA[i]), .B(BX[i]), .C(1'b1), .D(1'b1),
.CI(LE_CARRY),
.A(AA[i]), .B(BTOADDER[i]), .C(1'b1), .D(1'b1),
.CI(LE_CARRY[i]),
.SO(Y[i]),
.CO(ALM_CARRY[i+1])
.CO(LE_CARRY[i+1])
);
// ALM carry chain is not directly accessible, so calculate the carry through soft logic if really needed.
assign CO[i] = (AA[i] && BB[i]) || ((Y[i] ^ AA[i] ^ BB[i]) && (AA[i] || BB[i]));
end endgenerate
assign X = AA ^ BB;