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	Merge pull request #1868 from boqwxp/cleanup_delete
Clean up `passes/cmds/delete.cc`.
This commit is contained in:
		
						commit
						30934e425d
					
				
					 1 changed files with 19 additions and 24 deletions
				
			
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			@ -65,27 +65,24 @@ struct DeletePass : public Pass {
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		}
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		extra_args(args, argidx, design);
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		std::vector<RTLIL::IdString> delete_mods;
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		for (auto &mod_it : design->modules_)
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		std::vector<RTLIL::Module *> delete_mods;
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		for (auto module : design->modules())
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		{
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			if (design->selected_whole_module(mod_it.first) && !flag_input && !flag_output) {
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				delete_mods.push_back(mod_it.first);
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			if (design->selected_whole_module(module->name) && !flag_input && !flag_output) {
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				delete_mods.push_back(module);
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				continue;
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			}
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			if (!design->selected_module(mod_it.first))
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			if (!design->selected_module(module->name))
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				continue;
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			RTLIL::Module *module = mod_it.second;
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			if (flag_input || flag_output) {
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				for (auto &it : module->wires_)
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					if (design->selected(module, it.second)) {
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				for (auto wire : module->wires())
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					if (design->selected(module, wire)) {
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						if (flag_input)
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							it.second->port_input = false;
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							wire->port_input = false;
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						if (flag_output)
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							it.second->port_output = false;
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							wire->port_output = false;
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					}
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				module->fixup_ports();
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				continue;
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			@ -96,20 +93,19 @@ struct DeletePass : public Pass {
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			pool<RTLIL::IdString> delete_procs;
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			pool<RTLIL::IdString> delete_mems;
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			for (auto &it : module->wires_)
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				if (design->selected(module, it.second))
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					delete_wires.insert(it.second);
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			for (auto wire : module->selected_wires())
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				delete_wires.insert(wire);
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			for (auto &it : module->memories)
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				if (design->selected(module, it.second))
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					delete_mems.insert(it.first);
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			for (auto &it : module->cells_) {
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				if (design->selected(module, it.second))
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					delete_cells.insert(it.second);
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				if (it.second->type.in(ID($memrd), ID($memwr)) &&
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						delete_mems.count(it.second->parameters.at(ID::MEMID).decode_string()) != 0)
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					delete_cells.insert(it.second);
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			for (auto cell : module->cells()) {
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				if (design->selected(module, cell))
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					delete_cells.insert(cell);
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				if (cell->type.in(ID($memrd), ID($memwr)) &&
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						delete_mems.count(cell->parameters.at(ID::MEMID).decode_string()) != 0)
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					delete_cells.insert(cell);
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			}
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			for (auto &it : module->processes)
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			@ -134,9 +130,8 @@ struct DeletePass : public Pass {
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			module->fixup_ports();
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		}
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		for (auto &it : delete_mods) {
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			delete design->modules_.at(it);
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			design->modules_.erase(it);
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		for (auto mod : delete_mods) {
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			design->remove(mod);
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		}
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	}
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} DeletePass;
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