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Changes required for VPR place and route synth_xilinx.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
This commit is contained in:
Keith Rothman
parent
66fd6396d4
commit
3090951d54
12 changed files with 601 additions and 228 deletions
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@ -17,6 +17,9 @@
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*
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*/
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// ============================================================================
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// LCU
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(* techmap_celltype = "$lcu" *)
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module _80_xilinx_lcu (P, G, CI, CO);
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parameter WIDTH = 2;
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@ -28,10 +31,78 @@ module _80_xilinx_lcu (P, G, CI, CO);
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wire _TECHMAP_FAIL_ = WIDTH <= 2;
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genvar i;
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`ifdef _CLB_CARRY
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localparam CARRY4_COUNT = (WIDTH + 3) / 4;
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localparam MAX_WIDTH = CARRY4_COUNT * 4;
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localparam PAD_WIDTH = MAX_WIDTH - WIDTH;
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wire [MAX_WIDTH-1:0] S = {{PAD_WIDTH{1'b0}}, P & ~G};
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wire [MAX_WIDTH-1:0] C = CO;
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generate for (i = 0; i < CARRY4_COUNT; i = i + 1) begin:slice
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// Partially occupied CARRY4
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if ((i+1)*4 > WIDTH) begin
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// First one
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if (i == 0) begin
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CARRY4 carry4_1st_part
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(
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.CYINIT(CI),
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.CI (1'd0),
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.DI (G [(Y_WIDTH - 1):i*4]),
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.S (S [(Y_WIDTH - 1):i*4]),
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.CO (CO[(Y_WIDTH - 1):i*4]),
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);
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// Another one
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end else begin
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CARRY4 carry4_part
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(
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.CYINIT(1'd0),
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.CI (C [i*4 - 1]),
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.DI (G [(Y_WIDTH - 1):i*4]),
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.S (S [(Y_WIDTH - 1):i*4]),
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.CO (CO[(Y_WIDTH - 1):i*4]),
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);
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end
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// Fully occupied CARRY4
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end else begin
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// First one
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if (i == 0) begin
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CARRY4 carry4_1st_full
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(
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.CYINIT(CI),
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.CI (1'd0),
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.DI (G [((i+1)*4 - 1):i*4]),
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.S (S [((i+1)*4 - 1):i*4]),
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.CO (CO[((i+1)*4 - 1):i*4]),
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);
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// Another one
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end else begin
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CARRY4 carry4_full
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(
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.CYINIT(1'd0),
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.CI (C [i*4 - 1]),
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.DI (G [((i+1)*4 - 1):i*4]),
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.S (S [((i+1)*4 - 1):i*4]),
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.CO (CO[((i+1)*4 - 1):i*4]),
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);
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end
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end
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end endgenerate
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`elsif _EXPLICIT_CARRY
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wire [WIDTH-1:0] C = {CO, CI};
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wire [WIDTH-1:0] S = P & ~G;
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genvar i;
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generate for (i = 0; i < WIDTH; i = i + 1) begin:slice
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MUXCY muxcy (
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.CI(C[i]),
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@ -40,8 +111,28 @@ module _80_xilinx_lcu (P, G, CI, CO);
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.O(CO[i])
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);
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end endgenerate
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`else
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wire [WIDTH-1:0] C = {CO, CI};
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wire [WIDTH-1:0] S = P & ~G;
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generate for (i = 0; i < WIDTH; i = i + 1) begin:slice
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MUXCY muxcy (
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.CI(C[i]),
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.DI(G[i]),
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.S(S[i]),
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.O(CO[i])
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);
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end endgenerate
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`endif
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endmodule
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// ============================================================================
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// ALU
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(* techmap_celltype = "$alu" *)
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module _80_xilinx_alu (A, B, CI, BI, X, Y, CO);
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parameter A_SIGNED = 0;
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@ -49,6 +140,8 @@ module _80_xilinx_alu (A, B, CI, BI, X, Y, CO);
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parameter A_WIDTH = 1;
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parameter B_WIDTH = 1;
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parameter Y_WIDTH = 1;
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parameter _TECHMAP_CONSTVAL_CI_ = 0;
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parameter _TECHMAP_CONSTMSK_CI_ = 0;
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input [A_WIDTH-1:0] A;
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input [B_WIDTH-1:0] B;
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@ -66,16 +159,189 @@ module _80_xilinx_alu (A, B, CI, BI, X, Y, CO);
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wire [Y_WIDTH-1:0] AA = A_buf;
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wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;
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wire [Y_WIDTH-1:0] P = AA ^ BB;
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wire [Y_WIDTH-1:0] G = AA & BB;
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wire [Y_WIDTH-1:0] C = {CO, CI};
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wire [Y_WIDTH-1:0] S = P & ~G;
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genvar i;
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`ifdef _CLB_CARRY
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localparam CARRY4_COUNT = (Y_WIDTH + 3) / 4;
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localparam MAX_WIDTH = CARRY4_COUNT * 4;
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localparam PAD_WIDTH = MAX_WIDTH - Y_WIDTH;
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wire [MAX_WIDTH-1:0] S = {{PAD_WIDTH{1'b0}}, AA ^ BB};
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wire [MAX_WIDTH-1:0] DI = {{PAD_WIDTH{1'b0}}, AA & BB};
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wire [MAX_WIDTH-1:0] C = CO;
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genvar i;
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generate for (i = 0; i < CARRY4_COUNT; i = i + 1) begin:slice
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// Partially occupied CARRY4
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if ((i+1)*4 > Y_WIDTH) begin
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// First one
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if (i == 0) begin
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CARRY4 #(.IS_INITIALIZED(1'd1)) carry4_1st_part
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(
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.CYINIT(CI),
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.CI (1'd0),
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.DI (DI[(Y_WIDTH - 1):i*4]),
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.S (S [(Y_WIDTH - 1):i*4]),
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.O (Y [(Y_WIDTH - 1):i*4]),
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.CO (CO[(Y_WIDTH - 1):i*4])
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);
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// Another one
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end else begin
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CARRY4 carry4_part
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(
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.CYINIT(1'd0),
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.CI (C [i*4 - 1]),
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.DI (DI[(Y_WIDTH - 1):i*4]),
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.S (S [(Y_WIDTH - 1):i*4]),
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.O (Y [(Y_WIDTH - 1):i*4]),
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.CO (CO[(Y_WIDTH - 1):i*4])
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);
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end
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// Fully occupied CARRY4
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end else begin
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// First one
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if (i == 0) begin
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CARRY4 #(.IS_INITIALIZED(1'd1)) carry4_1st_full
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(
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.CYINIT(CI),
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.CI (1'd0),
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.DI (DI[((i+1)*4 - 1):i*4]),
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.S (S [((i+1)*4 - 1):i*4]),
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.O (Y [((i+1)*4 - 1):i*4]),
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.CO (CO[((i+1)*4 - 1):i*4])
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);
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// Another one
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end else begin
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CARRY4 carry4_full
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(
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.CYINIT(1'd0),
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.CI (C [i*4 - 1]),
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.DI (DI[((i+1)*4 - 1):i*4]),
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.S (S [((i+1)*4 - 1):i*4]),
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.O (Y [((i+1)*4 - 1):i*4]),
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.CO (CO[((i+1)*4 - 1):i*4])
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);
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end
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end
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end endgenerate
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`elsif _EXPLICIT_CARRY
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wire [Y_WIDTH-1:0] S = AA ^ BB;
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wire [Y_WIDTH-1:0] DI = AA & BB;
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wire CINIT;
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// Carry chain.
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//
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// VPR requires that the carry chain never hit the fabric. The CO input
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// to this techmap is the carry outputs for synthesis, e.g. might hit the
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// fabric.
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//
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// So we maintain two wire sets, CO_CHAIN is the carry that is for VPR,
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// e.g. off fabric dedicated chain. CO is the carry outputs that are
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// available to the fabric.
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wire [Y_WIDTH-1:0] CO_CHAIN;
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wire [Y_WIDTH-1:0] C = {CO_CHAIN, CINIT};
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// If carry chain is being initialized to a constant, techmap the constant
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// source. Otherwise techmap the fabric source.
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generate for (i = 0; i < 1; i = i + 1) begin:slice
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CARRY0 #(.CYINIT_FABRIC(1)) carry(
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.CI_INIT(CI),
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.DI(DI[0]),
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.S(S[0]),
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.CO_CHAIN(CO_CHAIN[0]),
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.CO_FABRIC(CO[0]),
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.O(Y[0])
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);
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end endgenerate
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generate for (i = 1; i < Y_WIDTH-1; i = i + 1) begin:slice
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if(i % 4 == 0) begin
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CARRY0 carry (
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.CI(C[i]),
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.DI(DI[i]),
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.S(S[i]),
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.CO_CHAIN(CO_CHAIN[i]),
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.CO_FABRIC(CO[i]),
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.O(Y[i])
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);
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end
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else
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begin
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CARRY carry (
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.CI(C[i]),
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.DI(DI[i]),
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.S(S[i]),
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.CO_CHAIN(CO_CHAIN[i]),
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.CO_FABRIC(CO[i]),
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.O(Y[i])
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);
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end
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end endgenerate
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generate for (i = Y_WIDTH-1; i < Y_WIDTH; i = i + 1) begin:slice
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if(i % 4 == 0) begin
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CARRY0 top_of_carry (
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.CI(C[i]),
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.DI(DI[i]),
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.S(S[i]),
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.CO_CHAIN(CO_CHAIN[i]),
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.O(Y[i])
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);
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end
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else
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begin
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CARRY top_of_carry (
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.CI(C[i]),
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.DI(DI[i]),
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.S(S[i]),
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.CO_CHAIN(CO_CHAIN[i]),
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.O(Y[i])
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);
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end
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// Turns out CO_FABRIC and O both use [ABCD]MUX, so provide
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// a non-congested path to output the top of the carry chain.
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// Registering the output of the CARRY block would solve this, but not
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// all designs do that.
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if((i+1) % 4 == 0) begin
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CARRY0 carry_output (
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.CI(CO_CHAIN[i]),
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.DI(0),
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.S(0),
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.O(CO[i])
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);
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end
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else
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begin
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CARRY carry_output (
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.CI(CO_CHAIN[i]),
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.DI(0),
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.S(0),
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.O(CO[i])
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);
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end
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end endgenerate
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`else
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wire [Y_WIDTH-1:0] S = AA ^ BB;
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wire [Y_WIDTH-1:0] DI = AA & BB;
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wire [Y_WIDTH-1:0] C = {CO, CI};
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generate for (i = 0; i < Y_WIDTH; i = i + 1) begin:slice
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MUXCY muxcy (
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.CI(C[i]),
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.DI(G[i]),
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.DI(DI[i]),
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.S(S[i]),
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.O(CO[i])
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);
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@ -86,6 +352,8 @@ module _80_xilinx_alu (A, B, CI, BI, X, Y, CO);
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);
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end endgenerate
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assign X = P;
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`endif
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assign X = S;
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endmodule
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