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iCE40 bram tests and fixes

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This commit is contained in:
Clifford Wolf 2015-04-24 08:32:07 +02:00
parent d6f7698f59
commit 308a59aa18
6 changed files with 181 additions and 16 deletions
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19
techlibs/ice40/tests/test_bram.v Normal file
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module bram #(
parameter ABITS = 8, DBITS = 8
) (
input clk,
input [ABITS-1:0] WR_ADDR,
input [DBITS-1:0] WR_DATA,
input WR_EN,
input [ABITS-1:0] RD_ADDR,
output reg [DBITS-1:0] RD_DATA
);
reg [DBITS-1:0] memory [0:2**ABITS-1];
always @(posedge clk) begin
if (WR_EN) memory[WR_ADDR] <= WR_DATA;
RD_DATA <= memory[RD_ADDR];
end
endmodule