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iCE40 bram tests and fixes

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This commit is contained in:
Clifford Wolf 2015-04-24 08:32:07 +02:00
parent d6f7698f59
commit 308a59aa18
6 changed files with 181 additions and 16 deletions
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1
techlibs/ice40/tests/.gitignore vendored
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test_ffs_[01][01][01][01][01]_*
test_bram_[0-9]*

17
techlibs/ice40/tests/test_bram.sh Normal file
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#!/bin/bash
set -ex
for abits in 7 8 9 10 11 12; do
for dbits in 2 4 8 16 24 32; do
id="test_bram_${abits}_${dbits}"
sed -e "s/ABITS = ./ABITS = $abits/g; s/DBITS = ./DBITS = $dbits/g;" < test_bram.v > ${id}.v
sed -e "s/ABITS = ./ABITS = $abits/g; s/DBITS = ./DBITS = $dbits/g;" < test_bram_tb.v > ${id}_tb.v
../../../yosys -ql ${id}_syn.log -p "synth_ice40" -o ${id}_syn.v ${id}.v
iverilog -s bram_tb -o ${id}_tb ${id}_syn.v ${id}_tb.v /opt/lscc/iCEcube2.2014.08/verilog/sb_ice_syn.v
# iverilog -s bram_tb -o ${id}_tb ${id}_syn.v ${id}_tb.v ../cells_sim.v
./${id}_tb > ${id}_tb.txt
if grep ERROR ${id}_tb.txt; then false; fi
done; done
echo OK

19
techlibs/ice40/tests/test_bram.v Normal file
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module bram #(
parameter ABITS = 8, DBITS = 8
) (
input clk,
input [ABITS-1:0] WR_ADDR,
input [DBITS-1:0] WR_DATA,
input WR_EN,
input [ABITS-1:0] RD_ADDR,
output reg [DBITS-1:0] RD_DATA
);
reg [DBITS-1:0] memory [0:2**ABITS-1];
always @(posedge clk) begin
if (WR_EN) memory[WR_ADDR] <= WR_DATA;
RD_DATA <= memory[RD_ADDR];
end
endmodule

105
techlibs/ice40/tests/test_bram_tb.v Normal file
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module bram_tb #(
parameter ABITS = 8, DBITS = 8
);
reg clk;
reg [ABITS-1:0] WR_ADDR;
reg [DBITS-1:0] WR_DATA;
reg WR_EN;
reg [ABITS-1:0] RD_ADDR;
wire [DBITS-1:0] RD_DATA;
bram uut (
.clk (clk ),
.WR_ADDR(WR_ADDR),
.WR_DATA(WR_DATA),
.WR_EN (WR_EN ),
.RD_ADDR(RD_ADDR),
.RD_DATA(RD_DATA)
);
reg [63:0] xorshift64_state = 64'd88172645463325252 ^ (ABITS << 24) ^ (DBITS << 16);
task xorshift64_next;
begin
// see page 4 of Marsaglia, George (July 2003). "Xorshift RNGs". Journal of Statistical Software 8 (14).
xorshift64_state = xorshift64_state ^ (xorshift64_state << 13);
xorshift64_state = xorshift64_state ^ (xorshift64_state >> 7);
xorshift64_state = xorshift64_state ^ (xorshift64_state << 17);
end
endtask
reg [ABITS-1:0] randaddr1;
reg [ABITS-1:0] randaddr2;
reg [ABITS-1:0] randaddr3;
function [31:0] getaddr(input [3:0] n);
begin
case (n)
0: getaddr = 0;
1: getaddr = 2**ABITS-1;
2: getaddr = 'b101 << (ABITS / 3);
3: getaddr = 'b101 << (2*ABITS / 3);
4: getaddr = 'b11011 << (ABITS / 4);
5: getaddr = 'b11011 << (2*ABITS / 4);
6: getaddr = 'b11011 << (3*ABITS / 4);
7: getaddr = randaddr1;
8: getaddr = randaddr2;
9: getaddr = randaddr3;
default: begin
getaddr = 1 << (2*n-16);
if (!getaddr) getaddr = xorshift64_state;
end
endcase
end
endfunction
reg [DBITS-1:0] memory [0:2**ABITS-1];
reg [DBITS-1:0] expected_rd, expected_rd_masked;
event error;
integer i, j;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, bram_tb);
xorshift64_next;
xorshift64_next;
xorshift64_next;
xorshift64_next;
randaddr1 = xorshift64_state;
xorshift64_next;
randaddr2 = xorshift64_state;
xorshift64_next;
randaddr3 = xorshift64_state;
xorshift64_next;
clk <= 0;
for (i = 0; i < 512; i = i+1) begin
WR_DATA <= xorshift64_state;
xorshift64_next;
WR_ADDR <= getaddr(i < 256 ? i[7:4] : xorshift64_state[63:60]);
xorshift64_next;
RD_ADDR <= getaddr(i < 256 ? i[3:0] : xorshift64_state[59:56]);
WR_EN <= xorshift64_state[55];
xorshift64_next;
#1; clk <= 1;
#1; clk <= 0;
expected_rd = memory[RD_ADDR];
if (WR_EN) memory[WR_ADDR] = WR_DATA;
for (j = 0; j < DBITS; j = j+1)
expected_rd_masked[j] = expected_rd[j] !== 1'bx ? expected_rd[j] : RD_DATA[j];
$display("#OUT# %3d | WA=%x WD=%x WE=%x | RA=%x RD=%x (%x) | %s", i, WR_ADDR, WR_DATA, WR_EN, RD_ADDR, RD_DATA, expected_rd, expected_rd_masked === RD_DATA ? "ok" : "ERROR");
if (expected_rd_masked !== RD_DATA) begin -> error; end
end
end
endmodule