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iCE40 bram tests and fixes
This commit is contained in:
Clifford Wolf
parent
d6f7698f59
commit
308a59aa18
6 changed files with 181 additions and 16 deletions
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@ -20,23 +20,23 @@ module \$__ICE40_RAM4K_M0 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
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case ({CLKPOL2, CLKPOL3})
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2'b00:
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SB_RAM40_4KNRNW #(.WRITE_MODE(0), .READ_MODE(0)) _TECHMAP_REPLACE_ (
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.RDATA(A1DATA), .RADDR(A1ADDR_11), .RCLK(CLK2), .RCLKE(1'b1), .RE(1'b1),
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.WDATA(B1DATA), .WADDR(B1ADDR_11), .WMASK(B1EN), .WCLK(CLK3), .WCLKE(1'b1), .WE(|B1EN)
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.RDATA(A1DATA), .RADDR(A1ADDR_11), .RCLK(CLK2), .RCLKE(1'b1), .RE(1'b1),
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.WDATA(B1DATA), .WADDR(B1ADDR_11), .MASK(B1EN), .WCLK(CLK3), .WCLKE(1'b1), .WE(|B1EN)
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);
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2'b01:
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SB_RAM40_4KNR #(.WRITE_MODE(0), .READ_MODE(0)) _TECHMAP_REPLACE_ (
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.RDATA(A1DATA), .RADDR(A1ADDR_11), .RCLK(CLK2), .RCLKE(1'b1), .RE(1'b1),
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.WDATA(B1DATA), .WADDR(B1ADDR_11), .WMASK(B1EN), .WCLK(CLK3), .WCLKE(1'b1), .WE(|B1EN)
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.RDATA(A1DATA), .RADDR(A1ADDR_11), .RCLK(CLK2), .RCLKE(1'b1), .RE(1'b1),
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.WDATA(B1DATA), .WADDR(B1ADDR_11), .MASK(B1EN), .WCLK(CLK3), .WCLKE(1'b1), .WE(|B1EN)
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);
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2'b10:
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SB_RAM40_4KNW #(.WRITE_MODE(0), .READ_MODE(0)) _TECHMAP_REPLACE_ (
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.RDATA(A1DATA), .RADDR(A1ADDR_11), .RCLK(CLK2), .RCLKE(1'b1), .RE(1'b1),
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.WDATA(B1DATA), .WADDR(B1ADDR_11), .WMASK(B1EN), .WCLK(CLK3), .WCLKE(1'b1), .WE(|B1EN)
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.RDATA(A1DATA), .RADDR(A1ADDR_11), .RCLK(CLK2), .RCLKE(1'b1), .RE(1'b1),
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.WDATA(B1DATA), .WADDR(B1ADDR_11), .MASK(B1EN), .WCLK(CLK3), .WCLKE(1'b1), .WE(|B1EN)
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);
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2'b11:
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SB_RAM40_4K #(.WRITE_MODE(0), .READ_MODE(0)) _TECHMAP_REPLACE_ (
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.RDATA(A1DATA), .RADDR(A1ADDR_11), .RCLK(CLK2), .RCLKE(1'b1), .RE(1'b1),
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.WDATA(B1DATA), .WADDR(B1ADDR_11), .WMASK(B1EN), .WCLK(CLK3), .WCLKE(1'b1), .WE(|B1EN)
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.RDATA(A1DATA), .RADDR(A1ADDR_11), .RCLK(CLK2), .RCLKE(1'b1), .RE(1'b1),
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.WDATA(B1DATA), .WADDR(B1ADDR_11), .MASK(B1EN), .WCLK(CLK3), .WCLKE(1'b1), .WE(|B1EN)
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);
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endcase
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endgenerate
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@ -305,20 +305,43 @@ module SB_RAM40_4K (
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always @(posedge WCLK) begin
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if (WE && WCLKE) begin
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if (WRITE_MODE == 0) begin
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for (i=0; i<16; i=i+1)
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if (MASK[i]) memory[WADDR[7:0]][i] <= WDATA[i];
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if (MASK[ 0]) memory[WADDR[7:0]][ 0] <= WDATA[ 0];
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if (MASK[ 1]) memory[WADDR[7:0]][ 1] <= WDATA[ 1];
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if (MASK[ 2]) memory[WADDR[7:0]][ 2] <= WDATA[ 2];
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if (MASK[ 3]) memory[WADDR[7:0]][ 3] <= WDATA[ 3];
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if (MASK[ 4]) memory[WADDR[7:0]][ 4] <= WDATA[ 4];
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if (MASK[ 5]) memory[WADDR[7:0]][ 5] <= WDATA[ 5];
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if (MASK[ 6]) memory[WADDR[7:0]][ 6] <= WDATA[ 6];
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if (MASK[ 7]) memory[WADDR[7:0]][ 7] <= WDATA[ 7];
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if (MASK[ 8]) memory[WADDR[7:0]][ 8] <= WDATA[ 8];
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if (MASK[ 9]) memory[WADDR[7:0]][ 9] <= WDATA[ 9];
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if (MASK[10]) memory[WADDR[7:0]][10] <= WDATA[10];
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if (MASK[11]) memory[WADDR[7:0]][11] <= WDATA[11];
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if (MASK[12]) memory[WADDR[7:0]][12] <= WDATA[12];
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if (MASK[13]) memory[WADDR[7:0]][13] <= WDATA[13];
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if (MASK[14]) memory[WADDR[7:0]][14] <= WDATA[14];
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if (MASK[15]) memory[WADDR[7:0]][15] <= WDATA[15];
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if (MASK[16]) memory[WADDR[7:0]][16] <= WDATA[16];
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end
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if (WRITE_MODE == 1) begin
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for (i=0; i<2; i=i+1)
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if (WADDR[0] == i) memory[WADDR[8:1]][i*8 +: 8] <= WDATA[i][7:0];
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if (WADDR[0] == 0) memory[WADDR[8:1]][0*8 +: 8] <= WDATA[7:0];
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if (WADDR[0] == 1) memory[WADDR[8:1]][1*8 +: 8] <= WDATA[7:0];
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end
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if (WRITE_MODE == 2) begin
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for (i=0; i<4; i=i+1)
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if (WADDR[1:0] == i) memory[WADDR[9:2]][i*4 +: 4] <= WDATA[i][3:0];
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if (WADDR[1:0] == 0) memory[WADDR[9:2]][0*4 +: 4] <= WDATA[3:0];
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if (WADDR[1:0] == 1) memory[WADDR[9:2]][1*4 +: 4] <= WDATA[3:0];
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if (WADDR[1:0] == 2) memory[WADDR[9:2]][2*4 +: 4] <= WDATA[3:0];
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if (WADDR[1:0] == 3) memory[WADDR[9:2]][3*4 +: 4] <= WDATA[3:0];
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end
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if (WRITE_MODE == 3) begin
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for (i=0; i<8; i=i+1)
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if (WADDR[2:0] == i) memory[WADDR[10:3]][i*2 +: 2] <= WDATA[i][1:0];
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if (WADDR[2:0] == 0) memory[WADDR[10:3]][0*2 +: 2] <= WDATA[1:0];
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if (WADDR[2:0] == 1) memory[WADDR[10:3]][1*2 +: 2] <= WDATA[1:0];
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if (WADDR[2:0] == 2) memory[WADDR[10:3]][2*2 +: 2] <= WDATA[1:0];
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if (WADDR[2:0] == 3) memory[WADDR[10:3]][3*2 +: 2] <= WDATA[1:0];
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if (WADDR[2:0] == 4) memory[WADDR[10:3]][4*2 +: 2] <= WDATA[1:0];
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if (WADDR[2:0] == 5) memory[WADDR[10:3]][5*2 +: 2] <= WDATA[1:0];
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if (WADDR[2:0] == 6) memory[WADDR[10:3]][6*2 +: 2] <= WDATA[1:0];
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if (WADDR[2:0] == 7) memory[WADDR[10:3]][7*2 +: 2] <= WDATA[1:0];
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end
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end
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end
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1
techlibs/ice40/tests/.gitignore
vendored
1
techlibs/ice40/tests/.gitignore
vendored
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@ -1 +1,2 @@
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test_ffs_[01][01][01][01][01]_*
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test_bram_[0-9]*
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17
techlibs/ice40/tests/test_bram.sh
Normal file
17
techlibs/ice40/tests/test_bram.sh
Normal file
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@ -0,0 +1,17 @@
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#!/bin/bash
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set -ex
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for abits in 7 8 9 10 11 12; do
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for dbits in 2 4 8 16 24 32; do
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id="test_bram_${abits}_${dbits}"
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sed -e "s/ABITS = ./ABITS = $abits/g; s/DBITS = ./DBITS = $dbits/g;" < test_bram.v > ${id}.v
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sed -e "s/ABITS = ./ABITS = $abits/g; s/DBITS = ./DBITS = $dbits/g;" < test_bram_tb.v > ${id}_tb.v
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../../../yosys -ql ${id}_syn.log -p "synth_ice40" -o ${id}_syn.v ${id}.v
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iverilog -s bram_tb -o ${id}_tb ${id}_syn.v ${id}_tb.v /opt/lscc/iCEcube2.2014.08/verilog/sb_ice_syn.v
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# iverilog -s bram_tb -o ${id}_tb ${id}_syn.v ${id}_tb.v ../cells_sim.v
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./${id}_tb > ${id}_tb.txt
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if grep ERROR ${id}_tb.txt; then false; fi
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done; done
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echo OK
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19
techlibs/ice40/tests/test_bram.v
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19
techlibs/ice40/tests/test_bram.v
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@ -0,0 +1,19 @@
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module bram #(
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parameter ABITS = 8, DBITS = 8
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) (
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input clk,
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input [ABITS-1:0] WR_ADDR,
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input [DBITS-1:0] WR_DATA,
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input WR_EN,
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input [ABITS-1:0] RD_ADDR,
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output reg [DBITS-1:0] RD_DATA
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);
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reg [DBITS-1:0] memory [0:2**ABITS-1];
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always @(posedge clk) begin
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if (WR_EN) memory[WR_ADDR] <= WR_DATA;
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RD_DATA <= memory[RD_ADDR];
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end
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endmodule
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105
techlibs/ice40/tests/test_bram_tb.v
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105
techlibs/ice40/tests/test_bram_tb.v
Normal file
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@ -0,0 +1,105 @@
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module bram_tb #(
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parameter ABITS = 8, DBITS = 8
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);
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reg clk;
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reg [ABITS-1:0] WR_ADDR;
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reg [DBITS-1:0] WR_DATA;
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reg WR_EN;
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reg [ABITS-1:0] RD_ADDR;
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wire [DBITS-1:0] RD_DATA;
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bram uut (
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.clk (clk ),
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.WR_ADDR(WR_ADDR),
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.WR_DATA(WR_DATA),
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.WR_EN (WR_EN ),
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.RD_ADDR(RD_ADDR),
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.RD_DATA(RD_DATA)
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);
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reg [63:0] xorshift64_state = 64'd88172645463325252 ^ (ABITS << 24) ^ (DBITS << 16);
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task xorshift64_next;
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begin
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// see page 4 of Marsaglia, George (July 2003). "Xorshift RNGs". Journal of Statistical Software 8 (14).
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xorshift64_state = xorshift64_state ^ (xorshift64_state << 13);
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xorshift64_state = xorshift64_state ^ (xorshift64_state >> 7);
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xorshift64_state = xorshift64_state ^ (xorshift64_state << 17);
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end
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endtask
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reg [ABITS-1:0] randaddr1;
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reg [ABITS-1:0] randaddr2;
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reg [ABITS-1:0] randaddr3;
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function [31:0] getaddr(input [3:0] n);
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begin
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case (n)
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0: getaddr = 0;
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1: getaddr = 2**ABITS-1;
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2: getaddr = 'b101 << (ABITS / 3);
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3: getaddr = 'b101 << (2*ABITS / 3);
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4: getaddr = 'b11011 << (ABITS / 4);
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5: getaddr = 'b11011 << (2*ABITS / 4);
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6: getaddr = 'b11011 << (3*ABITS / 4);
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7: getaddr = randaddr1;
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8: getaddr = randaddr2;
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9: getaddr = randaddr3;
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default: begin
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getaddr = 1 << (2*n-16);
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if (!getaddr) getaddr = xorshift64_state;
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end
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endcase
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end
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endfunction
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reg [DBITS-1:0] memory [0:2**ABITS-1];
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reg [DBITS-1:0] expected_rd, expected_rd_masked;
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event error;
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integer i, j;
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initial begin
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// $dumpfile("testbench.vcd");
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// $dumpvars(0, bram_tb);
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xorshift64_next;
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xorshift64_next;
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xorshift64_next;
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xorshift64_next;
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randaddr1 = xorshift64_state;
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xorshift64_next;
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randaddr2 = xorshift64_state;
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xorshift64_next;
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randaddr3 = xorshift64_state;
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xorshift64_next;
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clk <= 0;
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for (i = 0; i < 512; i = i+1) begin
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WR_DATA <= xorshift64_state;
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xorshift64_next;
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WR_ADDR <= getaddr(i < 256 ? i[7:4] : xorshift64_state[63:60]);
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xorshift64_next;
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RD_ADDR <= getaddr(i < 256 ? i[3:0] : xorshift64_state[59:56]);
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WR_EN <= xorshift64_state[55];
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xorshift64_next;
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#1; clk <= 1;
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#1; clk <= 0;
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expected_rd = memory[RD_ADDR];
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if (WR_EN) memory[WR_ADDR] = WR_DATA;
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for (j = 0; j < DBITS; j = j+1)
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expected_rd_masked[j] = expected_rd[j] !== 1'bx ? expected_rd[j] : RD_DATA[j];
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$display("#OUT# %3d | WA=%x WD=%x WE=%x | RA=%x RD=%x (%x) | %s", i, WR_ADDR, WR_DATA, WR_EN, RD_ADDR, RD_DATA, expected_rd, expected_rd_masked === RD_DATA ? "ok" : "ERROR");
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if (expected_rd_masked !== RD_DATA) begin -> error; end
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end
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end
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endmodule
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