mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-08-05 19:00:26 +00:00
Code Activity

xilinx: Add block RAM mapping for Virtex 2* and Spartan 3*.

Browse source
This commit is contained in:
Marcin Kościelnicki 2020-02-04 15:35:47 +01:00 • committed by Marcelina Kościelnicka
parent 95c46ccc55
commit 30854b9c7f
11 changed files with 370 additions and 1 deletions
Download patch file Download diff file Expand all files Collapse all files

2
techlibs/xilinx/xc7_brams_map.v
View file

@ -1,3 +1,5 @@
// Virtex 6 and Series 7 block RAM mapping.
module \$__XILINX_RAMB36_SDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
parameter CLKPOL2 = 1;
parameter CLKPOL3 = 1;