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xilinx: Add block RAM mapping for Virtex 2* and Spartan 3*.

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Marcin Kościelnicki 2020-02-04 15:35:47 +01:00 • committed by Marcelina Kościelnicka
parent 95c46ccc55
commit 30854b9c7f
11 changed files with 370 additions and 1 deletions
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techlibs/xilinx/xc6s_brams_map.v
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@ -1,3 +1,6 @@
// Spartan 3A DSP and Spartan 6 block RAM mapping (Spartan 6 is a superset of
// Spartan 3A DSP).
module \$__XILINX_RAMB8BWER_SDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
parameter CLKPOL2 = 1;
parameter CLKPOL3 = 1;