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xilinx: Add block RAM mapping for Virtex 2* and Spartan 3*.

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Marcin Kościelnicki 2020-02-04 15:35:47 +01:00 • committed by Marcelina Kościelnicka
parent 95c46ccc55
commit 30854b9c7f
11 changed files with 370 additions and 1 deletions
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31
techlibs/xilinx/xc2v_brams.txt Normal file
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# Virtex 2, Virtex 2 Pro, Spartan 3, Spartan 3E block RAM rules.
bram $__XILINX_RAMB16
init 1
abits 9 @a9d36
dbits 36 @a9d36
abits 10 @a10d18
dbits 18 @a10d18
abits 11 @a11d9
dbits 9 @a11d9
abits 12 @a12d4
dbits 4 @a12d4
abits 13 @a13d2
dbits 2 @a13d2
abits 14 @a14d1
dbits 1 @a14d1
groups 2
ports 1 1
wrmode 0 1
enable 1 1
transp 0 0
clocks 2 3
clkpol 2 3
endbram
match $__XILINX_RAMB16
min bits 4096
min efficiency 5
shuffle_enable B
make_transp
endmatch