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https://github.com/YosysHQ/yosys
synced 2025-04-28 11:25:53 +00:00
ql_dsp_*: Clean up
Clean up the code up to Yosys standards. Drop detection of QL_DSP2_MULTADD in io_regs since those cells can't be inferred with the current flow anyway.
This commit is contained in:
Martin Povišer
parent
6d7dafe5e5
commit
306e688406
2 changed files with 148 additions and 319 deletions
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@ -30,26 +30,24 @@ PRIVATE_NAMESPACE_BEGIN
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// ============================================================================
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struct QlDspIORegs : public Pass {
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const std::vector<std::string> ports2del_mult = {"load_acc", "subtract", "acc_fir", "dly_b"};
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const std::vector<std::string> ports2del_mult = {"load_acc", "subtract", "acc_fir", "dly_b",
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"saturate_enable", "shift_right", "round"};
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const std::vector<std::string> ports2del_mult_acc = {"acc_fir", "dly_b"};
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const std::vector<std::string> ports2del_mult_add = {"dly_b"};
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const std::vector<std::string> ports2del_extension = {"saturate_enable", "shift_right", "round"};
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/// Temporary SigBit to SigBit helper map.
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SigMap m_SigMap;
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SigMap sigmap;
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// ..........................................
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QlDspIORegs() : Pass("ql_dsp_io_regs", "Changes types of QL_DSP2/QL_DSP3 depending on their configuration.") {}
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QlDspIORegs() : Pass("ql_dsp_io_regs", "change types of QL_DSP2 depending on configuration") {}
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void help() override
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" ql_dsp_io_regs [options] [selection]\n");
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log("\n");
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log("Looks for QL_DSP2/QL_DSP3 cells and changes their types depending\n");
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log("on their configuration.\n");
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log("This pass looks for QL_DSP2 cells and changes their cell type depending on their\n");
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log("configuration.\n");
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}
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void execute(std::vector<std::string> a_Args, RTLIL::Design *a_Design) override
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@ -67,178 +65,92 @@ struct QlDspIORegs : public Pass {
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}
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}
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// Returns a pair of mask and value describing constant bit connections of
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// a SigSpec
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std::pair<uint32_t, uint32_t> get_constant_mask_value(const RTLIL::SigSpec *sigspec)
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{
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uint32_t mask = 0L;
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uint32_t value = 0L;
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auto sigbits = sigspec->bits();
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for (ssize_t i = (sigbits.size() - 1); i >= 0; --i) {
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auto other = m_SigMap(sigbits[i]);
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mask <<= 1;
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value <<= 1;
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// A known constant
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if (!other.is_wire() && other.data != RTLIL::Sx) {
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mask |= 0x1;
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value |= (other.data == RTLIL::S1);
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}
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}
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return std::make_pair(mask, value);
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}
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void ql_dsp_io_regs_pass(RTLIL::Module *module)
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{
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// Setup the SigMap
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m_SigMap.clear();
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m_SigMap.set(module);
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sigmap.set(module);
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for (auto cell : module->cells_) {
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std::string cell_type = cell.second->type.str();
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if (cell_type == RTLIL::escape_id("QL_DSP2") || cell_type == RTLIL::escape_id("QL_DSP3")) {
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auto dsp = cell.second;
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for (auto cell : module->cells()) {
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if (cell->type != ID(QL_DSP2))
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continue;
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// If the cell does not have the "is_inferred" attribute set
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// then don't touch it.
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if (!dsp->has_attribute(RTLIL::escape_id("is_inferred")) || dsp->get_bool_attribute(RTLIL::escape_id("is_inferred")) == false) {
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continue;
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}
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// If the cell does not have the "is_inferred" attribute set
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// then don't touch it.
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if (!cell->get_bool_attribute(ID(is_inferred)))
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continue;
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bool del_clk = true;
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bool use_dsp_cfg_params = (cell_type == RTLIL::escape_id("QL_DSP3"));
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// Get DSP configuration
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for (auto cfg_port : {ID(register_inputs), ID(output_select)})
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if (!cell->hasPort(cfg_port) || sigmap(cell->getPort(cfg_port)).is_fully_const())
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log_error("Missing or non-constant '%s' port on DSP cell %s\n",
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log_id(cfg_port), log_id(cell));
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int reg_in_i = sigmap(cell->getPort(ID(register_inputs))).as_int();
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int out_sel_i = sigmap(cell->getPort(ID(output_select))).as_int();
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int reg_in_i;
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int out_sel_i;
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// Get the feedback port
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if (!cell->hasPort(ID(feedback)))
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log_error("Missing 'feedback' port on %s", log_id(cell));
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SigSpec feedback = sigmap(cell->getPort(ID(feedback)));
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// Get DSP configuration
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if (use_dsp_cfg_params) {
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// Read MODE_BITS at correct indexes
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auto mode_bits = &dsp->getParam(RTLIL::escape_id("MODE_BITS"));
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RTLIL::Const register_inputs;
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register_inputs = mode_bits->bits.at(MODE_BITS_REGISTER_INPUTS_ID);
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reg_in_i = register_inputs.as_int();
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// Check the top two bits on 'feedback' to be constant zero.
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// That's what we are expecting from inference.
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if (feedback.extract(1, 2) != SigSpec(0, 2))
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log_error("Unexpected feedback configuration on %s\n", log_id(cell));
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RTLIL::Const output_select;
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output_select = mode_bits->extract(MODE_BITS_OUTPUT_SELECT_START_ID, MODE_BITS_OUTPUT_SELECT_WIDTH);
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out_sel_i = output_select.as_int();
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} else {
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// Read dedicated configuration ports
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const RTLIL::SigSpec *register_inputs;
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register_inputs = &dsp->getPort(RTLIL::escape_id("register_inputs"));
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if (!register_inputs)
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log_error("register_inputs port not found!");
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auto reg_in_c = register_inputs->as_const();
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reg_in_i = reg_in_c.as_int();
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// Build new type name
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std::string new_type = "QL_DSP2_MULT";
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const RTLIL::SigSpec *output_select;
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output_select = &dsp->getPort(RTLIL::escape_id("output_select"));
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if (!output_select)
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log_error("output_select port not found!");
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auto out_sel_c = output_select->as_const();
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out_sel_i = out_sel_c.as_int();
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}
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// Decide if we should be deleting the clock port
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bool del_clk = true;
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// Get the feedback port
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const RTLIL::SigSpec *feedback;
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feedback = &dsp->getPort(RTLIL::escape_id("feedback"));
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if (!feedback)
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log_error("feedback port not found!");
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// Check if feedback is or can be set to 0 which implies MACC
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auto feedback_con = get_constant_mask_value(feedback);
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bool have_macc = (feedback_con.second == 0x0);
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// log("mask=0x%08X value=0x%08X\n", consts.first, consts.second);
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// log_error("=== END HERE ===\n");
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// Build new type name
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std::string new_type = cell_type;
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new_type += "_MULT";
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if (have_macc) {
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switch (out_sel_i) {
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case 1:
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case 2:
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case 3:
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case 5:
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case 7:
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del_clk = false;
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new_type += "ACC";
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break;
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default:
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break;
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}
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} else {
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switch (out_sel_i) {
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case 1:
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case 2:
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case 3:
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case 5:
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case 7:
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new_type += "ADD";
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break;
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default:
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break;
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}
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}
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if (reg_in_i) {
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del_clk = false;
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new_type += "_REGIN";
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}
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if (out_sel_i > 3) {
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del_clk = false;
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new_type += "_REGOUT";
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}
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// Set new type name
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dsp->type = RTLIL::IdString(new_type);
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std::vector<std::string> ports2del;
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if (del_clk)
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ports2del.push_back("clk");
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switch (out_sel_i) {
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case 0:
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case 4:
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case 6:
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ports2del.insert(ports2del.end(), ports2del_mult.begin(), ports2del_mult.end());
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// Mark for deleton additional configuration ports
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if (!use_dsp_cfg_params) {
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ports2del.insert(ports2del.end(), ports2del_extension.begin(), ports2del_extension.end());
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}
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break;
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switch (out_sel_i) {
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case 1:
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case 2:
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case 3:
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case 5:
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case 7:
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if (have_macc) {
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ports2del.insert(ports2del.end(), ports2del_mult_acc.begin(), ports2del_mult_acc.end());
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} else {
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ports2del.insert(ports2del.end(), ports2del_mult_add.begin(), ports2del_mult_add.end());
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}
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del_clk = false;
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new_type += "ACC";
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break;
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}
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default:
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break;
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}
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for (auto portname : ports2del) {
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const RTLIL::SigSpec *port = &dsp->getPort(RTLIL::escape_id(portname));
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if (!port)
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log_error("%s port not found!", portname.c_str());
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dsp->connections_.erase(RTLIL::escape_id(portname));
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}
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if (reg_in_i) {
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del_clk = false;
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new_type += "_REGIN";
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}
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if (out_sel_i > 3) {
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del_clk = false;
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new_type += "_REGOUT";
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}
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// Set new type name
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cell->type = RTLIL::IdString(new_type);
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std::vector<std::string> ports2del;
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if (del_clk)
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cell->unsetPort(ID(clk));
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switch (out_sel_i) {
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case 0:
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case 4:
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case 6:
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for (auto port : ports2del_mult)
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cell->unsetPort(port);
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break;
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case 1:
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case 2:
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case 3:
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case 5:
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case 7:
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for (auto port : ports2del_mult_acc)
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cell->unsetPort(port);
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break;
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}
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}
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// Clear the sigmap
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m_SigMap.clear();
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}
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} QlDspIORegs;
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PRIVATE_NAMESPACE_END
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