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https://github.com/YosysHQ/yosys
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Improve libparse encapsulation
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parent
c35f5e379c
commit
3057c13a66
5 changed files with 73 additions and 71 deletions
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@ -226,7 +226,7 @@ static RTLIL::SigSpec create_tristate(RTLIL::Module *module, RTLIL::SigSpec func
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return cell->getPort(ID::Y);
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}
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static void create_ff(RTLIL::Module *module, LibertyAst *node)
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static void create_ff(RTLIL::Module *module, const LibertyAst *node)
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{
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RTLIL::SigSpec iq_sig(module->addWire(RTLIL::escape_id(node->args.at(0))));
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RTLIL::SigSpec iqn_sig(module->addWire(RTLIL::escape_id(node->args.at(1))));
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@ -303,7 +303,7 @@ static void create_ff(RTLIL::Module *module, LibertyAst *node)
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log_assert(!cell->type.empty());
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}
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static bool create_latch(RTLIL::Module *module, LibertyAst *node, bool flag_ignore_miss_data_latch)
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static bool create_latch(RTLIL::Module *module, const LibertyAst *node, bool flag_ignore_miss_data_latch)
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{
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RTLIL::SigSpec iq_sig(module->addWire(RTLIL::escape_id(node->args.at(0))));
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RTLIL::SigSpec iqn_sig(module->addWire(RTLIL::escape_id(node->args.at(1))));
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@ -422,7 +422,7 @@ static bool create_latch(RTLIL::Module *module, LibertyAst *node, bool flag_igno
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return true;
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}
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void parse_type_map(std::map<std::string, std::tuple<int, int, bool>> &type_map, LibertyAst *ast)
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void parse_type_map(std::map<std::string, std::tuple<int, int, bool>> &type_map, const LibertyAst *ast)
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{
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for (auto type_node : ast->children)
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{
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@ -604,7 +604,7 @@ struct LibertyFrontend : public Frontend {
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for (auto node : cell->children)
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{
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if (node->id == "pin" && node->args.size() == 1) {
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LibertyAst *dir = node->find("direction");
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const LibertyAst *dir = node->find("direction");
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if (!dir || (dir->value != "input" && dir->value != "output" && dir->value != "inout" && dir->value != "internal"))
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{
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if (!flag_ignore_miss_dir)
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@ -625,10 +625,10 @@ struct LibertyFrontend : public Frontend {
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if (!flag_lib)
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log_error("Error in cell %s: bus interfaces are only supported in -lib mode.\n", log_id(cell_name));
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LibertyAst *dir = node->find("direction");
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const LibertyAst *dir = node->find("direction");
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if (dir == nullptr) {
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LibertyAst *pin = node->find("pin");
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const LibertyAst *pin = node->find("pin");
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if (pin != nullptr)
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dir = pin->find("direction");
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}
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@ -639,7 +639,7 @@ struct LibertyFrontend : public Frontend {
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if (dir->value == "internal")
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continue;
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LibertyAst *bus_type_node = node->find("bus_type");
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const LibertyAst *bus_type_node = node->find("bus_type");
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if (!bus_type_node || !type_map.count(bus_type_node->value))
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log_error("Unknown or unsupported type for bus interface %s on cell %s.\n",
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@ -681,7 +681,7 @@ struct LibertyFrontend : public Frontend {
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{
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if (node->id == "pin" && node->args.size() == 1)
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{
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LibertyAst *dir = node->find("direction");
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const LibertyAst *dir = node->find("direction");
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if (flag_lib && dir->value == "internal")
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continue;
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@ -704,7 +704,7 @@ struct LibertyFrontend : public Frontend {
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if (flag_lib)
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continue;
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LibertyAst *func = node->find("function");
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const LibertyAst *func = node->find("function");
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if (func == NULL)
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{
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if (dir->value != "inout") { // allow inout with missing function, can be used for power pins
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@ -719,7 +719,7 @@ struct LibertyFrontend : public Frontend {
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}
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} else {
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RTLIL::SigSpec out_sig = parse_func_expr(module, func->value.c_str());
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LibertyAst *three_state = node->find("three_state");
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const LibertyAst *three_state = node->find("three_state");
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if (three_state) {
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out_sig = create_tristate(module, out_sig, three_state->value.c_str());
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}
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