mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-08-16 07:45:28 +00:00
Code Activity

anlogic: Use dfflegalize.

Browse source
This commit is contained in:
Marcelina Kościelnicka 2020-07-03 00:22:44 +02:00
parent 3d8d98d709
commit 3050454d6e
4 changed files with 49 additions and 62 deletions
Download patch file Download diff file Expand all files Collapse all files

45
techlibs/anlogic/cells_sim.v
View file

@ -10,9 +10,6 @@ module AL_MAP_SEQ (
parameter SRMUX = "SR"; //SR/INV
parameter SRMODE = "SYNC"; //SYNC/ASYNC
wire clk_ce;
assign clk_ce = ce ? clk : 1'b0;
wire srmux;
generate
case (SRMUX)
@ -20,7 +17,7 @@ module AL_MAP_SEQ (
"INV": assign srmux = ~sr;
default: assign srmux = sr;
endcase
endgenerate
endgenerate
wire regset;
generate
@ -34,43 +31,45 @@ module AL_MAP_SEQ (
initial q = regset;
generate
if (DFFMODE == "FF")
if (DFFMODE == "FF")
begin
if (SRMODE == "ASYNC")
if (SRMODE == "ASYNC")
begin
always @(posedge clk_ce, posedge srmux)
always @(posedge clk, posedge srmux)
if (srmux)
q <= regset;
else
q <= d;
end
else if (ce)
q <= d;
end
else
begin
always @(posedge clk_ce)
always @(posedge clk)
if (srmux)
q <= regset;
else
q <= d;
else if (ce)
q <= d;
end
end
else
begin
// DFFMODE == "LATCH"
if (SRMODE == "ASYNC")
if (SRMODE == "ASYNC")
begin
always @(clk_ce, srmux)
always @*
if (srmux)
q <= regset;
else
q <= d;
end
else if (~clk & ce)
q <= d;
end
else
begin
always @(clk_ce)
if (srmux)
q <= regset;
else
q <= d;
always @*
if (~clk) begin
if (srmux)
q <= regset;
else if (ce)
q <= d;
end
end
end
endgenerate