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Pack Y register

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This commit is contained in:
Eddie Hung 2019-07-22 15:05:16 -07:00
parent 5e70b8a22b
commit 304cefbbe2
2 changed files with 38 additions and 22 deletions
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12
passes/pmgen/ice40_dsp.pmg
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@ -143,17 +143,21 @@ endcode
match ffS
if muxAB
select ffS->type.in($dff)
select nusers(port(ffS, \D)) == 2
index <SigSpec> port(ffS, \D) === port(muxAB, \Y)
index <SigSpec> port(ffS, \Q) === sigS
filter nusers(port(muxAB, \Y)) == 2
filter includes(port(ffS, \D).to_sigbit_set(), port(muxAB, \Y).to_sigbit_set())
optional
endmatch
code clock clock_pol
code clock clock_pol sigS
if (ffS) {
SigBit c = port(ffS, \CLK).as_bit();
bool cp = param(ffS, \CLK_POLARITY).as_bool();
if (port(ffS, \Q) != sigS) {
sigS = port(muxAB, \Y);
sigS.replace(port(ffS, \D), port(ffS, \Q));
}
if (clock != SigBit() && (c != clock || cp != clock_pol))
reject;