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read_liberty: add cell context to more errors, remove log_id

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This commit is contained in:
Emil J. Tywoniak 2025-11-20 13:06:01 +01:00
parent 8ea51e1479
commit 302643330c
1 changed files with 17 additions and 17 deletions
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34
frontends/liberty/liberty.cc
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@ -40,14 +40,14 @@ static RTLIL::SigSpec parse_func_identifier(RTLIL::Module *module, const char *&
expr[id_len] == '_' || expr[id_len] == '[' || expr[id_len] == ']') id_len++; expr[id_len] == '_' || expr[id_len] == '[' || expr[id_len] == ']') id_len++;
if (id_len == 0) if (id_len == 0)
log_error("Expected identifier at `%s'.\n", expr); log_error("Expected identifier at `%s' in %s.\n", expr, RTLIL::unescape_id(module->name));
if (id_len == 1 && (*expr == '0' || *expr == '1')) if (id_len == 1 && (*expr == '0' || *expr == '1'))
return *(expr++) == '0' ? RTLIL::State::S0 : RTLIL::State::S1; return *(expr++) == '0' ? RTLIL::State::S0 : RTLIL::State::S1;
std::string id = RTLIL::escape_id(std::string(expr, id_len)); std::string id = RTLIL::escape_id(std::string(expr, id_len));
if (!module->wires_.count(id)) if (!module->wires_.count(id))
log_error("Can't resolve wire name %s.\n", RTLIL::unescape_id(id)); log_error("Can't resolve wire name %s in %s.\n", RTLIL::unescape_id(id), RTLIL::unescape_id(module->name));
expr += id_len; expr += id_len;
return module->wires_.at(id); return module->wires_.at(id);
@ -174,7 +174,7 @@ static RTLIL::SigSpec parse_func_expr(RTLIL::Module *module, const char *expr)
#endif #endif
if (stack.size() != 1 || stack.back().type != 3) if (stack.size() != 1 || stack.back().type != 3)
log_error("Parser error in function expr `%s'.\n", orig_expr); log_error("Parser error in function expr `%s'in %s.\n", orig_expr, RTLIL::unescape_id(module->name));
return stack.back().sig; return stack.back().sig;
} }
@ -211,7 +211,7 @@ static void create_ff(RTLIL::Module *module, const LibertyAst *node)
} }
if (clk_sig.size() == 0 || data_sig.size() == 0) if (clk_sig.size() == 0 || data_sig.size() == 0)
log_error("FF cell %s has no next_state and/or clocked_on attribute.\n", log_id(module->name)); log_error("FF cell %s has no next_state and/or clocked_on attribute.\n", RTLIL::unescape_id(module->name));
for (bool rerun_invert_rollback = true; rerun_invert_rollback;) for (bool rerun_invert_rollback = true; rerun_invert_rollback;)
{ {
@ -289,9 +289,9 @@ static bool create_latch(RTLIL::Module *module, const LibertyAst *node, bool fla
if (enable_sig.size() == 0 || data_sig.size() == 0) { if (enable_sig.size() == 0 || data_sig.size() == 0) {
if (!flag_ignore_miss_data_latch) if (!flag_ignore_miss_data_latch)
log_error("Latch cell %s has no data_in and/or enable attribute.\n", log_id(module->name)); log_error("Latch cell %s has no data_in and/or enable attribute.\n", RTLIL::unescape_id(module->name));
else else
log("Ignored latch cell %s with no data_in and/or enable attribute.\n", log_id(module->name)); log("Ignored latch cell %s with no data_in and/or enable attribute.\n", RTLIL::unescape_id(module->name));
return false; return false;
} }
@ -582,9 +582,9 @@ struct LibertyFrontend : public Frontend {
{ {
if (!flag_ignore_miss_dir) if (!flag_ignore_miss_dir)
{ {
log_error("Missing or invalid direction for pin %s on cell %s.\n", node->args.at(0), log_id(module->name)); log_error("Missing or invalid direction for pin %s on cell %s.\n", node->args.at(0), RTLIL::unescape_id(module->name));
} else { } else {
log("Ignoring cell %s with missing or invalid direction for pin %s.\n", log_id(module->name), node->args.at(0)); log("Ignoring cell %s with missing or invalid direction for pin %s.\n", RTLIL::unescape_id(module->name), node->args.at(0));
delete module; delete module;
goto skip_cell; goto skip_cell;
} }
@ -596,13 +596,13 @@ struct LibertyFrontend : public Frontend {
if (node->id == "bus" && node->args.size() == 1) if (node->id == "bus" && node->args.size() == 1)
{ {
if (flag_ignore_buses) { if (flag_ignore_buses) {
log("Ignoring cell %s with a bus interface %s.\n", log_id(module->name), node->args.at(0)); log("Ignoring cell %s with a bus interface %s.\n", RTLIL::unescape_id(module->name), node->args.at(0));
delete module; delete module;
goto skip_cell; goto skip_cell;
} }
if (!flag_lib) if (!flag_lib)
log_error("Error in cell %s: bus interfaces are only supported in -lib mode.\n", log_id(cell_name)); log_error("Error in cell %s: bus interfaces are only supported in -lib mode.\n", RTLIL::unescape_id(cell_name));
const LibertyAst *dir = node->find("direction"); const LibertyAst *dir = node->find("direction");
@ -613,7 +613,7 @@ struct LibertyFrontend : public Frontend {
} }
if (!dir || (dir->value != "input" && dir->value != "output" && dir->value != "inout" && dir->value != "internal")) if (!dir || (dir->value != "input" && dir->value != "output" && dir->value != "inout" && dir->value != "internal"))
log_error("Missing or invalid direction for bus %s on cell %s.\n", node->args.at(0), log_id(module->name)); log_error("Missing or invalid direction for bus %s on cell %s.\n", node->args.at(0), RTLIL::unescape_id(module->name));
simple_comb_cell = false; simple_comb_cell = false;
@ -624,7 +624,7 @@ struct LibertyFrontend : public Frontend {
if (!bus_type_node || !type_map.count(bus_type_node->value)) if (!bus_type_node || !type_map.count(bus_type_node->value))
log_error("Unknown or unsupported type for bus interface %s on cell %s.\n", log_error("Unknown or unsupported type for bus interface %s on cell %s.\n",
node->args.at(0).c_str(), log_id(cell_name)); node->args.at(0).c_str(), RTLIL::unescape_id(cell_name));
int bus_type_width = std::get<0>(type_map.at(bus_type_node->value)); int bus_type_width = std::get<0>(type_map.at(bus_type_node->value));
int bus_type_offset = std::get<1>(type_map.at(bus_type_node->value)); int bus_type_offset = std::get<1>(type_map.at(bus_type_node->value));
@ -701,9 +701,9 @@ struct LibertyFrontend : public Frontend {
if (dir->value != "inout") { // allow inout with missing function, can be used for power pins if (dir->value != "inout") { // allow inout with missing function, can be used for power pins
if (!flag_ignore_miss_func) if (!flag_ignore_miss_func)
{ {
log_error("Missing function on output %s of cell %s.\n", log_id(wire->name), log_id(module->name)); log_error("Missing function on output %s of cell %s.\n", RTLIL::unescape_id(wire->name), RTLIL::unescape_id(module->name));
} else { } else {
log("Ignoring cell %s with missing function on output %s.\n", log_id(module->name), log_id(wire->name)); log("Ignoring cell %s with missing function on output %s.\n", RTLIL::unescape_id(module->name), RTLIL::unescape_id(wire->name));
delete module; delete module;
goto skip_cell; goto skip_cell;
} }
@ -757,13 +757,13 @@ struct LibertyFrontend : public Frontend {
if (design->has(cell_name)) { if (design->has(cell_name)) {
Module *existing_mod = design->module(cell_name); Module *existing_mod = design->module(cell_name);
if (!flag_nooverwrite && !flag_overwrite && !existing_mod->get_bool_attribute(ID::blackbox)) { if (!flag_nooverwrite && !flag_overwrite && !existing_mod->get_bool_attribute(ID::blackbox)) {
log_error("Re-definition of cell/module %s!\n", log_id(cell_name)); log_error("Re-definition of cell/module %s!\n", RTLIL::unescape_id(cell_name));
} else if (flag_nooverwrite) { } else if (flag_nooverwrite) {
log("Ignoring re-definition of module %s.\n", log_id(cell_name)); log("Ignoring re-definition of module %s.\n", RTLIL::unescape_id(cell_name));
delete module; delete module;
goto skip_cell; goto skip_cell;
} else { } else {
log("Replacing existing%s module %s.\n", existing_mod->get_bool_attribute(ID::blackbox) ? " blackbox" : "", log_id(cell_name)); log("Replacing existing%s module %s.\n", existing_mod->get_bool_attribute(ID::blackbox) ? " blackbox" : "", RTLIL::unescape_id(cell_name));
design->remove(existing_mod); design->remove(existing_mod);
} }
} }