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abc9_ops: discard $__ABC9_DELAY boxes
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aaafd784a5
commit
300003cb78
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@ -572,17 +572,12 @@ void reintegrate(RTLIL::Module *module)
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log_assert(r.second);
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log_assert(r.second);
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}
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}
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pool<IdString> delay_boxes;
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std::vector<Cell*> boxes;
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std::vector<Cell*> boxes;
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for (auto cell : module->cells().to_vector()) {
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for (auto cell : module->cells().to_vector()) {
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if (cell->has_keep_attr())
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if (cell->has_keep_attr())
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continue;
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continue;
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if (cell->type.in(ID($_AND_), ID($_NOT_), ID($__ABC9_FF_)))
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if (cell->type.in(ID($_AND_), ID($_NOT_), ID($__ABC9_FF_), ID($__ABC9_DELAY)))
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module->remove(cell);
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module->remove(cell);
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else if (cell->type.begins_with("$paramod$__ABC9_DELAY\\DELAY=")) {
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delay_boxes.insert(cell->name);
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module->remove(cell);
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}
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else if (cell->attributes.erase("\\abc9_box_seq"))
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else if (cell->attributes.erase("\\abc9_box_seq"))
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boxes.emplace_back(cell);
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boxes.emplace_back(cell);
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}
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}
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@ -674,7 +669,7 @@ void reintegrate(RTLIL::Module *module)
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bit_drivers[i].insert(mapped_cell->name);
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bit_drivers[i].insert(mapped_cell->name);
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}
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}
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}
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}
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else if (delay_boxes.count(mapped_cell->name)) {
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else if (mapped_cell->type == ID($__ABC9_DELAY)) {
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SigBit I = mapped_cell->getPort(ID(i));
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SigBit I = mapped_cell->getPort(ID(i));
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SigBit O = mapped_cell->getPort(ID(o));
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SigBit O = mapped_cell->getPort(ID(o));
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if (I.wire)
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if (I.wire)
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