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More changes to simlib to make it friendlier to a wider range of tools

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This commit is contained in:
Clifford Wolf 2014-01-18 19:13:43 +01:00
parent 4a9e133fab
commit 2fbaaaca7a
1 changed files with 14 additions and 10 deletions
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16
techlibs/common/simlib.v
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@ -65,10 +65,10 @@ parameter Y_WIDTH = 0;
output [Y_WIDTH-1:0] Y; output [Y_WIDTH-1:0] Y;
generate generate
if (!A_SIGNED && 0 < A_WIDTH && A_WIDTH < Y_WIDTH) begin:A if (!A_SIGNED && 0 < A_WIDTH && A_WIDTH < Y_WIDTH) begin:BLOCK1
assign Y[A_WIDTH-1:0] = A_BUF.val; assign Y[A_WIDTH-1:0] = A_BUF.val;
assign Y[Y_WIDTH-1:A_WIDTH] = 0; assign Y[Y_WIDTH-1:A_WIDTH] = 0;
end else begin:B end else begin:BLOCK2
assign Y = +A_BUF.val; assign Y = +A_BUF.val;
end end
endgenerate endgenerate
@ -953,8 +953,10 @@ input [ABITS-1:0] ADDR;
output [WIDTH-1:0] DATA; output [WIDTH-1:0] DATA;
initial begin initial begin
if (MEMID != "") begin
$display("ERROR: Found non-simulatable instance of $memrd!"); $display("ERROR: Found non-simulatable instance of $memrd!");
$finish; $finish;
end
end end
endmodule endmodule
@ -975,8 +977,10 @@ input [ABITS-1:0] ADDR;
input [WIDTH-1:0] DATA; input [WIDTH-1:0] DATA;
initial begin initial begin
if (MEMID != "") begin
$display("ERROR: Found non-simulatable instance of $memwr!"); $display("ERROR: Found non-simulatable instance of $memwr!");
$finish; $finish;
end
end end
endmodule endmodule
@ -1008,7 +1012,7 @@ input [WR_PORTS*ABITS-1:0] WR_ADDR;
input [WR_PORTS*WIDTH-1:0] WR_DATA; input [WR_PORTS*WIDTH-1:0] WR_DATA;
reg [WIDTH-1:0] data [SIZE-1:0]; reg [WIDTH-1:0] data [SIZE-1:0];
event update_async_rd; reg update_async_rd;
genvar i; genvar i;
generate generate
@ -1032,7 +1036,7 @@ generate
always @(WR_ADDR or WR_DATA or WR_EN) begin always @(WR_ADDR or WR_DATA or WR_EN) begin
if (WR_EN[i]) begin if (WR_EN[i]) begin
data[ WR_ADDR[ (i+1)*ABITS-1 : i*ABITS ] - OFFSET ] <= WR_DATA[ (i+1)*WIDTH-1 : i*WIDTH ]; data[ WR_ADDR[ (i+1)*ABITS-1 : i*ABITS ] - OFFSET ] <= WR_DATA[ (i+1)*WIDTH-1 : i*WIDTH ];
#1 -> update_async_rd; update_async_rd <= 1; update_async_rd <= 0;
end end
end end
end else end else
@ -1040,13 +1044,13 @@ generate
always @(posedge WR_CLK[i]) always @(posedge WR_CLK[i])
if (WR_EN[i]) begin if (WR_EN[i]) begin
data[ WR_ADDR[ (i+1)*ABITS-1 : i*ABITS ] - OFFSET ] <= WR_DATA[ (i+1)*WIDTH-1 : i*WIDTH ]; data[ WR_ADDR[ (i+1)*ABITS-1 : i*ABITS ] - OFFSET ] <= WR_DATA[ (i+1)*WIDTH-1 : i*WIDTH ];
#1 -> update_async_rd; update_async_rd <= 1; update_async_rd <= 0;
end end
end else begin:rd_negclk end else begin:rd_negclk
always @(negedge WR_CLK[i]) always @(negedge WR_CLK[i])
if (WR_EN[i]) begin if (WR_EN[i]) begin
data[ WR_ADDR[ (i+1)*ABITS-1 : i*ABITS ] - OFFSET ] <= WR_DATA[ (i+1)*WIDTH-1 : i*WIDTH ]; data[ WR_ADDR[ (i+1)*ABITS-1 : i*ABITS ] - OFFSET ] <= WR_DATA[ (i+1)*WIDTH-1 : i*WIDTH ];
#1 -> update_async_rd; update_async_rd <= 1; update_async_rd <= 0;
end end
end end
end end