mirror of
				https://github.com/YosysHQ/yosys
				synced 2025-11-04 13:29:12 +00:00 
			
		
		
		
	Revert "add MUX support"
It turns out that they make everything worse and they don't PnR.
This reverts commit 3eff2271d0.
			
			
This commit is contained in:
		
							parent
							
								
									96efa63f16
								
							
						
					
					
						commit
						2fb20f184a
					
				
					 3 changed files with 0 additions and 17 deletions
				
			
		| 
						 | 
					@ -50,9 +50,6 @@ module  \$__DFFE_PP0 (input D, C, R, E, output Q); DFFCE _TECHMAP_REPLACE_ (.D(D
 | 
				
			||||||
module  \$__DFFE_PN0 (input D, C, R, E, output Q); DFFCE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(!R), .CE(E)); endmodule
 | 
					module  \$__DFFE_PN0 (input D, C, R, E, output Q); DFFCE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(!R), .CE(E)); endmodule
 | 
				
			||||||
 | 
					
 | 
				
			||||||
 | 
					
 | 
				
			||||||
module  \$_MUX_ (input A, B, S, output Y); MUX2  _TECHMAP_REPLACE_ (.I0(A), .I1(B), .S0(S), .O(Y)); endmodule
 | 
					 | 
				
			||||||
module  \$_MUX4_ (input A, B, C, D, S, T, output Y); MUX4  _TECHMAP_REPLACE_ (.I0(A), .I1(B), .I2(C), .I3(D), .S0(S), .S1(T), .O(Y)); endmodule
 | 
					 | 
				
			||||||
 | 
					 | 
				
			||||||
module \$lut (A, Y);
 | 
					module \$lut (A, Y);
 | 
				
			||||||
  parameter WIDTH = 0;
 | 
					  parameter WIDTH = 0;
 | 
				
			||||||
  parameter LUT = 0;
 | 
					  parameter LUT = 0;
 | 
				
			||||||
| 
						 | 
					
 | 
				
			||||||
| 
						 | 
					@ -24,19 +24,6 @@ module LUT4(output F, input I0, I1, I2, I3);
 | 
				
			||||||
	assign F = I0 ? s1[1] : s1[0];
 | 
						assign F = I0 ? s1[1] : s1[0];
 | 
				
			||||||
endmodule
 | 
					endmodule
 | 
				
			||||||
 | 
					
 | 
				
			||||||
module MUX2 (I0, I1, S0, O);
 | 
					 | 
				
			||||||
input I0, I1, S0;
 | 
					 | 
				
			||||||
output O;
 | 
					 | 
				
			||||||
assign O = S0 ? I1 : I0;
 | 
					 | 
				
			||||||
endmodule
 | 
					 | 
				
			||||||
 | 
					 | 
				
			||||||
module MUX4 (I0, I1, I2, I3, S0, S1, O);
 | 
					 | 
				
			||||||
input I0, I1, I2, I3, S0, S1;
 | 
					 | 
				
			||||||
output O;
 | 
					 | 
				
			||||||
assign O = S1 ? (S0 ? I3 : I2) :
 | 
					 | 
				
			||||||
                (S0 ? I1 : I0);
 | 
					 | 
				
			||||||
endmodule
 | 
					 | 
				
			||||||
 | 
					 | 
				
			||||||
module DFF (output reg Q, input CLK, D);
 | 
					module DFF (output reg Q, input CLK, D);
 | 
				
			||||||
	parameter [0:0] INIT = 1'b0;
 | 
						parameter [0:0] INIT = 1'b0;
 | 
				
			||||||
	initial Q = INIT;
 | 
						initial Q = INIT;
 | 
				
			||||||
| 
						 | 
					
 | 
				
			||||||
| 
						 | 
					@ -196,7 +196,6 @@ struct SynthGowinPass : public ScriptPass
 | 
				
			||||||
			run("opt_clean");
 | 
								run("opt_clean");
 | 
				
			||||||
			if (!nodffe)
 | 
								if (!nodffe)
 | 
				
			||||||
				run("dff2dffe -direct-match $_DFF_* -direct-match $__DFFS_*");
 | 
									run("dff2dffe -direct-match $_DFF_* -direct-match $__DFFS_*");
 | 
				
			||||||
			run("muxcover -mux4");
 | 
					 | 
				
			||||||
			run("techmap -map +/gowin/cells_map.v");
 | 
								run("techmap -map +/gowin/cells_map.v");
 | 
				
			||||||
			run("opt_expr -mux_undef");
 | 
								run("opt_expr -mux_undef");
 | 
				
			||||||
			run("simplemap");
 | 
								run("simplemap");
 | 
				
			||||||
| 
						 | 
					
 | 
				
			||||||
		Loading…
	
	Add table
		Add a link
		
	
		Reference in a new issue