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Some improvements in fsm_opt and fsm_map for FSM with unreachable states
This commit is contained in:
Clifford Wolf
parent
51aa5544fb
commit
2faef89738
3 changed files with 104 additions and 52 deletions
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@ -207,65 +207,72 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module)
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// generate next_state signal
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RTLIL::Wire *next_state_onehot = module->addWire(NEW_ID, fsm_data.state_table.size());
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for (size_t i = 0; i < fsm_data.state_table.size(); i++)
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if (SIZE(fsm_data.state_table) == 1)
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{
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std::map<RTLIL::Const, std::set<int>> pattern_cache;
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std::set<int> fullstate_cache;
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for (size_t j = 0; j < fsm_data.state_table.size(); j++)
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fullstate_cache.insert(j);
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for (auto &tr : fsm_data.transition_table) {
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if (tr.state_out == int(i))
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pattern_cache[tr.ctrl_in].insert(tr.state_in);
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else
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fullstate_cache.erase(tr.state_in);
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}
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implement_pattern_cache(module, pattern_cache, fullstate_cache, fsm_data.state_table.size(), state_onehot, ctrl_in, RTLIL::SigSpec(next_state_onehot, i));
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}
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if (encoding_is_onehot)
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{
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RTLIL::SigSpec next_state_sig(RTLIL::State::Sm, next_state_wire->width);
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for (size_t i = 0; i < fsm_data.state_table.size(); i++) {
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RTLIL::Const state = fsm_data.state_table[i];
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int bit_idx = -1;
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for (size_t j = 0; j < state.bits.size(); j++)
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if (state.bits[j] == RTLIL::State::S1)
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bit_idx = j;
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if (bit_idx >= 0)
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next_state_sig.replace(bit_idx, RTLIL::SigSpec(next_state_onehot, i));
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}
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log_assert(!next_state_sig.has_marked_bits());
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module->connect(RTLIL::SigSig(next_state_wire, next_state_sig));
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module->connect(next_state_wire, fsm_data.state_table.front());
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}
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else
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{
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RTLIL::SigSpec sig_a, sig_b, sig_s;
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int reset_state = fsm_data.reset_state;
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if (reset_state < 0)
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reset_state = 0;
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RTLIL::Wire *next_state_onehot = module->addWire(NEW_ID, fsm_data.state_table.size());
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for (size_t i = 0; i < fsm_data.state_table.size(); i++) {
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RTLIL::Const state = fsm_data.state_table[i];
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if (int(i) == fsm_data.reset_state) {
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sig_a = RTLIL::SigSpec(state);
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} else {
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sig_b.append(RTLIL::SigSpec(state));
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sig_s.append(RTLIL::SigSpec(next_state_onehot, i));
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for (size_t i = 0; i < fsm_data.state_table.size(); i++)
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{
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std::map<RTLIL::Const, std::set<int>> pattern_cache;
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std::set<int> fullstate_cache;
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for (size_t j = 0; j < fsm_data.state_table.size(); j++)
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fullstate_cache.insert(j);
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for (auto &tr : fsm_data.transition_table) {
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if (tr.state_out == int(i))
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pattern_cache[tr.ctrl_in].insert(tr.state_in);
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else
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fullstate_cache.erase(tr.state_in);
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}
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implement_pattern_cache(module, pattern_cache, fullstate_cache, fsm_data.state_table.size(), state_onehot, ctrl_in, RTLIL::SigSpec(next_state_onehot, i));
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}
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RTLIL::Cell *mux_cell = module->addCell(NEW_ID, "$safe_pmux");
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mux_cell->setPort("\\A", sig_a);
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mux_cell->setPort("\\B", sig_b);
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mux_cell->setPort("\\S", sig_s);
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mux_cell->setPort("\\Y", RTLIL::SigSpec(next_state_wire));
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mux_cell->parameters["\\WIDTH"] = RTLIL::Const(sig_a.size());
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mux_cell->parameters["\\S_WIDTH"] = RTLIL::Const(sig_s.size());
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if (encoding_is_onehot)
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{
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RTLIL::SigSpec next_state_sig(RTLIL::State::Sm, next_state_wire->width);
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for (size_t i = 0; i < fsm_data.state_table.size(); i++) {
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RTLIL::Const state = fsm_data.state_table[i];
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int bit_idx = -1;
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for (size_t j = 0; j < state.bits.size(); j++)
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if (state.bits[j] == RTLIL::State::S1)
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bit_idx = j;
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if (bit_idx >= 0)
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next_state_sig.replace(bit_idx, RTLIL::SigSpec(next_state_onehot, i));
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}
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log_assert(!next_state_sig.has_marked_bits());
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module->connect(RTLIL::SigSig(next_state_wire, next_state_sig));
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}
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else
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{
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RTLIL::SigSpec sig_a, sig_b, sig_s;
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int reset_state = fsm_data.reset_state;
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if (reset_state < 0)
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reset_state = 0;
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for (size_t i = 0; i < fsm_data.state_table.size(); i++) {
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RTLIL::Const state = fsm_data.state_table[i];
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if (int(i) == fsm_data.reset_state) {
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sig_a = RTLIL::SigSpec(state);
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} else {
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sig_b.append(RTLIL::SigSpec(state));
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sig_s.append(RTLIL::SigSpec(next_state_onehot, i));
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}
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}
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RTLIL::Cell *mux_cell = module->addCell(NEW_ID, "$safe_pmux");
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mux_cell->setPort("\\A", sig_a);
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mux_cell->setPort("\\B", sig_b);
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mux_cell->setPort("\\S", sig_s);
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mux_cell->setPort("\\Y", RTLIL::SigSpec(next_state_wire));
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mux_cell->parameters["\\WIDTH"] = RTLIL::Const(sig_a.size());
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mux_cell->parameters["\\S_WIDTH"] = RTLIL::Const(sig_s.size());
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}
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}
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// Generate ctrl_out signal
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@ -30,6 +30,48 @@ struct FsmOpt
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FsmData fsm_data;
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RTLIL::Cell *cell;
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RTLIL::Module *module;
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void opt_unreachable_states()
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{
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while (1)
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{
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std::set<int> unreachable_states;
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std::vector<FsmData::transition_t> new_transition_table;
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std::vector<RTLIL::Const> new_state_table;
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std::map<int, int> old_to_new_state;
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for (int i = 0; i < SIZE(fsm_data.state_table); i++)
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if (i != fsm_data.reset_state)
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unreachable_states.insert(i);
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for (auto &trans : fsm_data.transition_table)
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unreachable_states.erase(trans.state_out);
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if (unreachable_states.empty())
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break;
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for (int i = 0; i < SIZE(fsm_data.state_table); i++) {
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if (unreachable_states.count(i)) {
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log(" Removing unreachable state %s.\n", log_signal(fsm_data.state_table[i]));
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continue;
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}
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old_to_new_state[i] = SIZE(new_state_table);
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new_state_table.push_back(fsm_data.state_table[i]);
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}
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for (auto trans : fsm_data.transition_table) {
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if (unreachable_states.count(trans.state_in))
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continue;
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trans.state_in = old_to_new_state.at(trans.state_in);
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trans.state_out = old_to_new_state.at(trans.state_out);
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new_transition_table.push_back(trans);
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}
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new_transition_table.swap(fsm_data.transition_table);
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new_state_table.swap(fsm_data.state_table);
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fsm_data.reset_state = old_to_new_state.at(fsm_data.reset_state);
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}
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}
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bool signal_is_unused(RTLIL::SigSpec sig)
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{
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@ -253,6 +295,8 @@ struct FsmOpt
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this->cell = cell;
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this->module = module;
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opt_unreachable_states();
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opt_unused_outputs();
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opt_alias_inputs();
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@ -17,7 +17,8 @@ python generate.py
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idx=$( printf "%05d" $i )
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echo "temp/uut_${idx}.log: temp/uut_${idx}.ys temp/uut_${idx}.v"
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echo " @echo -n '[$i]'"
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echo " @../../yosys -ql temp/uut_${idx}.log temp/uut_${idx}.ys"
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echo " @../../yosys -ql temp/uut_${idx}.out temp/uut_${idx}.ys"
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echo " @mv temp/uut_${idx}.out temp/uut_${idx}.log"
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echo " @grep -q 'SAT proof finished' temp/uut_${idx}.log && echo -n K || echo -n T"
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all_targets="$all_targets temp/uut_${idx}.log"
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done
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