From c1459bc748d0d2c47dcb2366e5a0893736d6d463 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 30 Aug 2019 12:22:14 -0700 Subject: [PATCH 1/7] Do not restrict multiplier to unsigned --- passes/pmgen/ice40_dsp.cc | 5 ----- 1 file changed, 5 deletions(-) diff --git a/passes/pmgen/ice40_dsp.cc b/passes/pmgen/ice40_dsp.cc index 39d033a04..16bfe537f 100644 --- a/passes/pmgen/ice40_dsp.cc +++ b/passes/pmgen/ice40_dsp.cc @@ -64,11 +64,6 @@ void create_ice40_dsp(ice40_dsp_pm &pm) bool mul_signed = st.mul->getParam("\\A_SIGNED").as_bool(); - if (mul_signed) { - log(" inference of signed iCE40 DSP arithmetic is currently not supported.\n"); - return; - } - log(" replacing $mul with SB_MAC16 cell.\n"); Cell *cell = pm.module->addCell(NEW_ID, "\\SB_MAC16"); From 76a52712dac4f28fbc3c5611911310d252cd91a6 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 30 Aug 2019 12:22:59 -0700 Subject: [PATCH 2/7] Improve tests/ice40/macc.ys for SB_MAC16 --- tests/ice40/macc.v | 4 ++-- tests/ice40/macc.ys | 13 ++++++++----- 2 files changed, 10 insertions(+), 7 deletions(-) diff --git a/tests/ice40/macc.v b/tests/ice40/macc.v index 63a3d3a74..6c3676c83 100644 --- a/tests/ice40/macc.v +++ b/tests/ice40/macc.v @@ -2,8 +2,8 @@ Example from: https://www.latticesemi.com/-/media/LatticeSemi/Documents/UserManuals/EI/iCEcube201701UserGuide.ashx?document_id=52071 [p. 77]. */ module top(clk,a,b,c,set); -parameter A_WIDTH = 4; -parameter B_WIDTH = 3; +parameter A_WIDTH = 6 /*4*/; +parameter B_WIDTH = 6 /*3*/; input set; input clk; input signed [(A_WIDTH - 1):0] a; diff --git a/tests/ice40/macc.ys b/tests/ice40/macc.ys index fe5b5f662..0f4c19be5 100644 --- a/tests/ice40/macc.ys +++ b/tests/ice40/macc.ys @@ -1,10 +1,13 @@ read_verilog macc.v proc hierarchy -top top -equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -dsp # equivalency check +#equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -dsp # equivalency check + +equiv_opt -run :prove -map +/ice40/cells_sim.v synth_ice40 -dsp +async2sync +equiv_opt -run prove: -assert null + design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module -select -assert-count 38 t:SB_LUT4 -select -assert-count 3 t:SB_CARRY -select -assert-count 7 t:SB_DFFSR -select -assert-none t:SB_LUT4 t:SB_CARRY t:SB_DFFSR %% t:* %D +select -assert-count 1 t:SB_MAC16 +select -assert-none t:SB_MAC16 %% t:* %D From 17b77fd41197b64f79bbbb59088e9de623d84716 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 30 Aug 2019 14:00:40 -0700 Subject: [PATCH 3/7] Missing dep for test_pmgen --- passes/pmgen/Makefile.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/passes/pmgen/Makefile.inc b/passes/pmgen/Makefile.inc index e73a7b1c9..4989c582a 100644 --- a/passes/pmgen/Makefile.inc +++ b/passes/pmgen/Makefile.inc @@ -4,7 +4,7 @@ # -------------------------------------- OBJS += passes/pmgen/test_pmgen.o -passes/pmgen/test_pmgen.o: passes/pmgen/test_pmgen_pm.h passes/pmgen/ice40_dsp_pm.h passes/pmgen/peepopt_pm.h +passes/pmgen/test_pmgen.o: passes/pmgen/test_pmgen_pm.h passes/pmgen/ice40_dsp_pm.h passes/pmgen/peepopt_pm.h passes/pmgen/xilinx_srl_pm.h $(eval $(call add_extra_objs,passes/pmgen/test_pmgen_pm.h)) # -------------------------------------- From 90b44113d89cd1f028e7805e0990dae43e2efa6f Mon Sep 17 00:00:00 2001 From: David Shah Date: Sat, 31 Aug 2019 09:58:46 +0100 Subject: [PATCH 4/7] ecp5_gsr: Fix typo Signed-off-by: David Shah --- techlibs/ecp5/ecp5_gsr.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/techlibs/ecp5/ecp5_gsr.cc b/techlibs/ecp5/ecp5_gsr.cc index 8b8927d31..2bc714b6f 100644 --- a/techlibs/ecp5/ecp5_gsr.cc +++ b/techlibs/ecp5/ecp5_gsr.cc @@ -124,7 +124,7 @@ struct Ecp5GsrPass : public Pass { SigBit lsr = sigmap(sig_lsr[0]); if (!inverted_gsr.count(lsr)) continue; - cell->setParam(ID(SRMODE), Const("SYNC")); + cell->setParam(ID(SRMODE), Const("LSR_OVER_CE")); cell->unsetPort(ID(LSR)); } From a3c16a05657e639a04d647a15af56b6fbce25e17 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Sat, 31 Aug 2019 11:12:06 +0200 Subject: [PATCH 5/7] Fix TRELLIS_FF simulation model --- techlibs/ecp5/cells_sim.v | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v index 75a1aad1f..5bdb8395e 100644 --- a/techlibs/ecp5/cells_sim.v +++ b/techlibs/ecp5/cells_sim.v @@ -229,14 +229,15 @@ module TRELLIS_FF(input CLK, LSR, CE, DI, M, output reg Q); parameter REGSET = "RESET"; parameter [127:0] LSRMODE = "LSR"; - reg muxce; - always @(*) + wire muxce; + generate case (CEMUX) - "1": muxce = 1'b1; - "0": muxce = 1'b0; - "INV": muxce = ~CE; - default: muxce = CE; + "1": assign muxce = 1'b1; + "0": assign muxce = 1'b0; + "INV": assign muxce = ~CE; + default: assign muxce = CE; endcase + endgenerate wire muxlsr = (LSRMUX == "INV") ? ~LSR : LSR; wire muxclk = (CLKMUX == "INV") ? ~CLK : CLK; From fa5065e9b5ed58d774bfe4fc23de681314b50270 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Sun, 1 Sep 2019 11:00:09 +0200 Subject: [PATCH 6/7] Fix select command error msg, fixes issue #1081 --- passes/cmds/select.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/passes/cmds/select.cc b/passes/cmds/select.cc index 59d10a1b8..0f1f05ccb 100644 --- a/passes/cmds/select.cc +++ b/passes/cmds/select.cc @@ -664,7 +664,7 @@ static void select_stmt(RTLIL::Design *design, std::string arg) } else if (arg == "%D") { if (work_stack.size() < 2) - log_cmd_error("Must have at least two elements on the stack for operator %%d.\n"); + log_cmd_error("Must have at least two elements on the stack for operator %%D.\n"); select_op_diff(design, work_stack[work_stack.size()-1], work_stack[work_stack.size()-2]); work_stack[work_stack.size()-2] = work_stack[work_stack.size()-1]; work_stack.pop_back(); @@ -693,7 +693,7 @@ static void select_stmt(RTLIL::Design *design, std::string arg) } else if (arg == "%C") { if (work_stack.size() < 1) - log_cmd_error("Must have at least one element on the stack for operator %%M.\n"); + log_cmd_error("Must have at least one element on the stack for operator %%C.\n"); select_op_module_to_cells(design, work_stack[work_stack.size()-1]); } else if (arg == "%c") { From f76cb584940fa3217de28febdb103443b8a8cf37 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 30 Aug 2019 20:15:09 -0700 Subject: [PATCH 7/7] Recognise built-in types (e.g. $_DFF_*) --- backends/aiger/xaiger.cc | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index 77d0e94c2..e1b84236d 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -261,11 +261,12 @@ struct XAigerWriter } } else { - bool cell_known = cell->known(); + bool cell_known = inst_module || cell->known(); for (const auto &c : cell->connections()) { if (c.second.is_fully_const()) continue; - auto is_input = !cell_known || cell->input(c.first); - auto is_output = !cell_known || cell->output(c.first); + auto port_wire = inst_module ? inst_module->wire(c.first) : nullptr; + auto is_input = (port_wire && port_wire->port_input) || !cell_known || cell->input(c.first); + auto is_output = (port_wire && port_wire->port_output) || !cell_known || cell->output(c.first); if (!is_input && !is_output) log_error("Connection '%s' on cell '%s' (type '%s') not recognised!\n", log_id(c.first), log_id(cell), log_id(cell->type));