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https://github.com/YosysHQ/yosys
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$mem cell in verilog backend : grouped writes by clock
This commit is contained in:
luke whittlesey
parent
a8fe040906
commit
2f90499e3d
2 changed files with 110 additions and 58 deletions
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@ -38,7 +38,7 @@
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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bool norename, noattr, attr2comment, noexpr, nomem;
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bool norename, noattr, attr2comment, noexpr;
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int auto_name_counter, auto_name_offset, auto_name_digits;
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std::map<RTLIL::IdString, int> auto_name_map;
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std::set<RTLIL::IdString> reg_wires, reg_ct;
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@ -791,7 +791,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
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return true;
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}
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if (cell->type == "$mem" && nomem == false)
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if (cell->type == "$mem")
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{
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RTLIL::IdString memid = cell->parameters["\\MEMID"].decode_string();
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std::string mem_id = id(cell->parameters["\\MEMID"].decode_string());
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@ -818,6 +818,13 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
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f << stringf("%s" "end\n", indent.c_str());
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}
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// create a map : "edge clk" -> expressions within that clock domain
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dict<std::string, std::vector<std::string>> clk_to_lof_body;
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clk_to_lof_body[""] = std::vector<std::string>();
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std::string clk_domain_str;
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// create a list of reg declarations
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std::vector<std::string> lof_reg_declarations;
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int nread_ports = cell->parameters["\\RD_PORTS"].as_int();
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RTLIL::SigSpec sig_rd_clk, sig_rd_data, sig_rd_addr;
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bool use_rd_clk, rd_clk_posedge, rd_transparent;
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@ -830,6 +837,13 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
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use_rd_clk = cell->parameters["\\RD_CLK_ENABLE"].extract(i).as_bool();
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rd_clk_posedge = cell->parameters["\\RD_CLK_POLARITY"].extract(i).as_bool();
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rd_transparent = cell->parameters["\\RD_TRANSPARENT"].extract(i).as_bool();
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{
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std::ostringstream os;
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dump_sigspec(os, sig_rd_clk);
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clk_domain_str = stringf("%sedge %s", rd_clk_posedge ? "pos" : "neg", os.str().c_str());
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if( clk_to_lof_body.count(clk_domain_str) == 0 )
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clk_to_lof_body[clk_domain_str] = std::vector<std::string>();
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}
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if (use_rd_clk && !rd_transparent)
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{
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// for clocked read ports make something like:
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@ -838,16 +852,19 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
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// temp_id <= array_reg[r_addr];
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// assign r_data = temp_id;
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std::string temp_id = next_auto_id();
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f << stringf("%s" "reg [%d:0] %s;\n", indent.c_str(), sig_rd_data.size() - 1, temp_id.c_str());
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f << stringf("%s" "always @(%sedge ", indent.c_str(), rd_clk_posedge ? "pos" : "neg");
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dump_sigspec(f, sig_rd_clk);
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f << stringf(")\n");
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f << stringf("%s" " %s <= %s[", indent.c_str(), temp_id.c_str(), mem_id.c_str());
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dump_sigspec(f, sig_rd_addr);
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f << stringf("];\n");
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f << stringf("%s" "assign ", indent.c_str());
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dump_sigspec(f, sig_rd_data);
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f << stringf(" = %s;\n", temp_id.c_str());
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lof_reg_declarations.push_back( stringf("reg [%d:0] %s;\n", sig_rd_data.size() - 1, temp_id.c_str()) );
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{
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std::ostringstream os;
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dump_sigspec(os, sig_rd_addr);
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std::string line = stringf("%s <= %s[%s];\n", temp_id.c_str(), mem_id.c_str(), os.str().c_str());
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clk_to_lof_body[clk_domain_str].push_back(line);
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}
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{
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std::ostringstream os;
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dump_sigspec(os, sig_rd_data);
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std::string line = stringf("assign %s = %s;\n", os.str().c_str(), temp_id.c_str());
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clk_to_lof_body[""].push_back(line);
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}
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} else {
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if (rd_transparent) {
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// for rd-transparent read-ports make something like:
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@ -856,24 +873,27 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
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// temp_id <= r_addr;
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// assign r_data = array_reg[temp_id];
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std::string temp_id = next_auto_id();
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f << stringf("%s" "reg [%d:0] %s;\n", indent.c_str(), sig_rd_addr.size() - 1, temp_id.c_str());
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f << stringf("%s" "always @(%sedge ", indent.c_str(), rd_clk_posedge ? "pos" : "neg");
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dump_sigspec(f, sig_rd_clk);
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f << stringf(")\n");
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f << stringf("%s" " %s <= ", indent.c_str(), temp_id.c_str());
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dump_sigspec(f, sig_rd_addr);
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f << stringf(";\n");
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f << stringf("%s" "assign ", indent.c_str());
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dump_sigspec(f, sig_rd_data);
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f << stringf(" = %s[%s];\n", mem_id.c_str(), temp_id.c_str());
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lof_reg_declarations.push_back( stringf("reg [%d:0] %s;\n", sig_rd_addr.size() - 1, temp_id.c_str()) );
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{
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std::ostringstream os;
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dump_sigspec(os, sig_rd_addr);
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std::string line = stringf("%s <= %s;\n", temp_id.c_str(), os.str().c_str());
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clk_to_lof_body[clk_domain_str].push_back(line);
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}
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{
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std::ostringstream os;
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dump_sigspec(os, sig_rd_data);
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std::string line = stringf("assign %s = %s[%s];\n", os.str().c_str(), mem_id.c_str(), temp_id.c_str());
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clk_to_lof_body[clk_domain_str].push_back(line);
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}
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} else {
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// for non-clocked read-ports make something like:
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// assign r_data = array_reg[r_addr];
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f << stringf("%s" "assign ", indent.c_str());
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dump_sigspec(f, sig_rd_data);
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f << stringf(" = %s[", mem_id.c_str());
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dump_sigspec(f, sig_rd_addr);
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f << stringf("];\n");
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std::ostringstream os, os2;
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dump_sigspec(os, sig_rd_data);
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dump_sigspec(os2, sig_rd_addr);
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std::string line = stringf("assign %s = %s[%s];\n", os.str().c_str(), mem_id.c_str(), os2.str().c_str());
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clk_to_lof_body[""].push_back(line);
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}
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}
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}
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@ -889,16 +909,19 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
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// write ports
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for (int i=0; i < nwrite_ports; i++)
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{
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// for write-ports make something like:
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// always @(posedge clk)
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// if (wr_en)
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// memid[w_addr] <= w_data;
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sig_wr_clk = cell->getPort("\\WR_CLK").extract(i);
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sig_wr_data = cell->getPort("\\WR_DATA").extract(i*width, width);
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sig_wr_addr = cell->getPort("\\WR_ADDR").extract(i*abits, abits);
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sig_wr_en = cell->getPort("\\WR_EN").extract(i*width, width);
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sig_wr_en_bit = sig_wr_en.extract(0);
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wr_clk_posedge = cell->parameters["\\WR_CLK_POLARITY"].extract(i).as_bool();
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{
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std::ostringstream os;
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dump_sigspec(os, sig_wr_clk);
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clk_domain_str = stringf("%sedge %s", wr_clk_posedge ? "pos" : "neg", os.str().c_str());
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if( clk_to_lof_body.count(clk_domain_str) == 0 )
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clk_to_lof_body[clk_domain_str] = std::vector<std::string>();
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}
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// group the wen bits
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last_bit = sig_wr_en.extract(0);
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lof_wen = RTLIL::SigSpec(last_bit);
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@ -916,35 +939,75 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
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}
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// make something like:
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// always @(posedge clk)
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// if (wr_en_bit)
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// memid[w_addr][??] <= w_data[??];
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// if (wr_en_bit) memid[w_addr][??] <= w_data[??];
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// ...
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n = 0;
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for (auto &wen_bit : lof_wen) {
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wen_width = wen_to_width[wen_bit];
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if (!(wen_bit == RTLIL::SigBit(false)))
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{
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f << stringf("%s" "always @(%sedge ", indent.c_str(), wr_clk_posedge ? "pos" : "neg");
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dump_sigspec(f, sig_wr_clk);
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f << stringf(")\n");
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std::ostringstream os;
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if (!(wen_bit == RTLIL::SigBit(true)))
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{
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f << stringf("%s" " if (", indent.c_str());
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dump_sigspec(f, wen_bit);
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f << stringf(")\n ");
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os << stringf("if (");
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dump_sigspec(os, wen_bit);
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os << stringf(") ");
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}
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f << stringf("%s" " %s[", indent.c_str(), mem_id.c_str());
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dump_sigspec(f, sig_wr_addr);
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os << stringf("%s[", mem_id.c_str());
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dump_sigspec(os, sig_wr_addr);
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if (wen_width == width)
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f << stringf("] <= ");
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os << stringf("] <= ");
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else
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f << stringf("][%d:%d] <= ", n+wen_width-1, n);
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dump_sigspec(f, sig_wr_data.extract(n, wen_width));
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f << stringf(";\n");
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os << stringf("][%d:%d] <= ", n+wen_width-1, n);
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dump_sigspec(os, sig_wr_data.extract(n, wen_width));
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os << stringf(";\n");
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clk_to_lof_body[clk_domain_str].push_back(os.str());
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}
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n += wen_width;
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}
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}
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// Output verilog that looks something like this:
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// reg [..] _3_;
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// always @(posedge CLK2) begin
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// _3_ <= memory[D1ADDR];
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// if (A1EN)
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// memory[A1ADDR] <= A1DATA;
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// if (A2EN)
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// memory[A2ADDR] <= A2DATA;
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// ...
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// end
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// always @(negedge CLK1) begin
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// if (C1EN)
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// memory[C1ADDR] <= C1DATA;
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// end
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// ...
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// assign D1DATA = _3_;
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// assign D2DATA <= memory[D2ADDR];
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// the reg ... definitions
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for(auto ® : lof_reg_declarations)
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{
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f << stringf("%s" "%s", indent.c_str(), reg.c_str());
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}
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// the block of expressions by clock domain
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for(auto &pair : clk_to_lof_body)
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{
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std::string clk_domain = pair.first;
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std::vector<std::string> lof_lines = pair.second;
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if( clk_domain != "")
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{
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f << stringf("%s" "always @(%s) begin\n", indent.c_str(), clk_domain.c_str());
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for(auto &line : lof_lines)
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f << stringf("%s%s" "%s", indent.c_str(), indent.c_str(), line.c_str());
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f << stringf("%s" "end\n", indent.c_str());
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}
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else
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{
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// the non-clocked assignments
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for(auto &line : lof_lines)
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f << stringf("%s" "%s", indent.c_str(), line.c_str());
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}
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}
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return true;
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}
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@ -1285,10 +1348,6 @@ struct VerilogBackend : public Backend {
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log(" only write selected modules. modules must be selected entirely or\n");
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log(" not at all.\n");
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log("\n");
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log(" -nomem\n");
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log(" do not create verilog code for $mem cells. This is only used for\n");
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log(" testing.\n");
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log("\n");
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}
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virtual void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design)
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{
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@ -1298,7 +1357,6 @@ struct VerilogBackend : public Backend {
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noattr = false;
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attr2comment = false;
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noexpr = false;
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nomem = false;
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bool blackboxes = false;
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bool selected = false;
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@ -1356,10 +1414,6 @@ struct VerilogBackend : public Backend {
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selected = true;
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continue;
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}
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if (arg == "-nomem") {
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nomem = true;
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continue;
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}
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break;
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}
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extra_args(f, filename, args, argidx);
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