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verifix: fix bits() deprecation warnings

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This commit is contained in:
Miodrag Milanovic 2025-10-13 09:47:18 +02:00
parent 9a12d92551
commit 2f8f421dee
2 changed files with 11 additions and 12 deletions
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21
frontends/verific/verific.cc
View file

@ -1663,7 +1663,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma
if (*ascii_initdata == 0) if (*ascii_initdata == 0)
break; break;
if (*ascii_initdata == '0' || *ascii_initdata == '1') { if (*ascii_initdata == '0' || *ascii_initdata == '1') {
initval.bits()[bit_idx] = (*ascii_initdata == '0') ? State::S0 : State::S1; initval.set(bit_idx, (*ascii_initdata == '0') ? State::S0 : State::S1);
initval_valid = true; initval_valid = true;
} }
ascii_initdata++; ascii_initdata++;
@ -1787,9 +1787,9 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma
if (init_nets.count(net)) { if (init_nets.count(net)) {
if (init_nets.at(net) == '0') if (init_nets.at(net) == '0')
initval.bits().at(bitidx) = State::S0; initval.set(bitidx, State::S0);
if (init_nets.at(net) == '1') if (init_nets.at(net) == '1')
initval.bits().at(bitidx) = State::S1; initval.set(bitidx, State::S1);
initval_valid = true; initval_valid = true;
init_nets.erase(net); init_nets.erase(net);
} }
@ -1862,13 +1862,12 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma
if (bit.wire->attributes.count(ID::init)) if (bit.wire->attributes.count(ID::init))
initval = bit.wire->attributes.at(ID::init); initval = bit.wire->attributes.at(ID::init);
while (GetSize(initval) < GetSize(bit.wire)) initval.resize(GetSize(bit.wire), State::Sx);
initval.bits().push_back(State::Sx);
if (it.second == '0') if (it.second == '0')
initval.bits().at(bit.offset) = State::S0; initval.set(bit.offset, State::S0);
if (it.second == '1') if (it.second == '1')
initval.bits().at(bit.offset) = State::S1; initval.set(bit.offset, State::S1);
bit.wire->attributes[ID::init] = initval; bit.wire->attributes[ID::init] = initval;
} }
@ -2055,7 +2054,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma
} }
Const qx_init = Const(State::S1, width); Const qx_init = Const(State::S1, width);
qx_init.bits().resize(2 * width, State::S0); qx_init.resize(2 * width, State::S0);
clocking.addDff(new_verific_id(inst), sig_dx, sig_qx, qx_init); clocking.addDff(new_verific_id(inst), sig_dx, sig_qx, qx_init);
module->addXnor(new_verific_id(inst), sig_dx, sig_qx, sig_ox); module->addXnor(new_verific_id(inst), sig_dx, sig_qx, sig_ox);
@ -2320,7 +2319,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma
continue; continue;
if (non_ff_bits.count(SigBit(wire, i))) if (non_ff_bits.count(SigBit(wire, i)))
initval.bits()[i] = State::Sx; initval.set(i, State::Sx);
} }
if (wire->port_input) { if (wire->port_input) {
@ -2513,7 +2512,7 @@ Cell *VerificClocking::addDff(IdString name, SigSpec sig_d, SigSpec sig_q, Const
if (c.wire && c.wire->attributes.count(ID::init)) { if (c.wire && c.wire->attributes.count(ID::init)) {
Const val = c.wire->attributes.at(ID::init); Const val = c.wire->attributes.at(ID::init);
for (int i = 0; i < GetSize(c); i++) for (int i = 0; i < GetSize(c); i++)
initval.bits()[offset+i] = val[c.offset+i]; initval.set(offset+i, val[c.offset+i]);
} }
offset += GetSize(c); offset += GetSize(c);
} }
@ -2584,7 +2583,7 @@ Cell *VerificClocking::addAldff(IdString name, RTLIL::SigSpec sig_aload, RTLIL::
if (c.wire && c.wire->attributes.count(ID::init)) { if (c.wire && c.wire->attributes.count(ID::init)) {
Const val = c.wire->attributes.at(ID::init); Const val = c.wire->attributes.at(ID::init);
for (int i = 0; i < GetSize(c); i++) for (int i = 0; i < GetSize(c); i++)
initval.bits()[offset+i] = val[c.offset+i]; initval.set(offset+i, val[c.offset+i]);
} }
offset += GetSize(c); offset += GetSize(c);
} }

2
frontends/verific/verificsva.cc
View file

@ -577,7 +577,7 @@ struct SvaFsm
if (delta_pos >= 0 && i_within_j && j_within_i) { if (delta_pos >= 0 && i_within_j && j_within_i) {
did_something = true; did_something = true;
values[i].bits()[delta_pos] = State::Sa; values[i].set(delta_pos, State::Sa);
values[j] = values.back(); values[j] = values.back();
values.pop_back(); values.pop_back();
goto next_pair; goto next_pair;