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Add reference to source of Tclktoq timing

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Eddie Hung 2019-08-19 12:39:22 -07:00
parent 91687d3fea
commit 2f86366087
1 changed files with 2 additions and 0 deletions
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techlibs/xilinx/abc_ff.v
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@ -20,6 +20,8 @@
// ============================================================================
// Max delays from https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L237-L251
module FDRE (output reg Q, input C, CE, D, R);
parameter [0:0] INIT = 1'b0;
parameter [0:0] IS_C_INVERTED = 1'b0;